AT90USB647-MU Atmel, AT90USB647-MU Datasheet - Page 337

• Manufacturer Part Number: AT90USB647-MU
• Description: MCU, 8BIT, 64K FLASH, USB, 64QFN
• Manufacturer: Atmel

Specifications of AT90USB647-MU

• Controller Family/series: AT90
• No. Of I/o's: 48
• Eeprom Memory Size: 2KB
• Ram Memory Size: 4KB
• Cpu Speed: 16MHz
• No. Of: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 64KB
• Oscillator Type: External, Internal
• Package: 64QFN EP
• Device Core: AVR
• Family Name: AT90
• Maximum Speed: 20 MHz
• Ram Size: 4 KB
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 48
• Interface Type: SPI/TWI/USART/USB
• On-chip Adc: 8-chx10-bit
• Operating Temperature: -40 to 85 °C
• Number Of Timers: 4
• Lead Free Status / Rohs Status: Details

26.7
26.7.1
26.8
26.9
7593K–AVR–11/09
On-chip Debug Related Register in I/O Memory
Using the JTAG Programming Capabilities
Bibliography
On-chip Debug Register – OCDR
The OCDR Register provides a communication channel from the running program in the micro-
controller to the debugger. The CPU can transfer a byte to the debugger by writing to this
location. At the same time, an internal flag; I/O Debug Register Dirty – IDRD – is set to indicate
to the debugger that the register has been written. When the CPU reads the OCDR Register the
7 LSB will be from the OCDR Register, while the MSB is the IDRD bit. The debugger clears the
IDRD bit when it has read the information.
In some AVR devices, this register is shared with a standard I/O location. In this case, the OCDR
Register can only be accessed if the OCDEN Fuse is programmed, and the debugger enables
access to the OCDR Register. In all other cases, the standard I/O location is accessed.
Refer to the debugger documentation for further information on how to use this register.
Programming of AVR parts via JTAG is performed via the 4-pin JTAG port, TCK, TMS, TDI, and
TDO. These are the only pins that need to be controlled/observed to perform JTAG program-
ming (in addition to power pins). It is not required to apply 12V externally. The JTAGEN Fuse
must be programmed and the JTD bit in the MCUCR Register must be cleared to enable the
JTAG Test Access Port.
The JTAG programming capability supports:
The Lock bit security is exactly as in parallel programming mode. If the Lock bits LB1 or LB2 are
programmed, the OCDEN Fuse cannot be programmed unless first doing a chip erase. This is a
security feature that ensures no back-door exists for reading out the content of a secured
device.
The details on programming through the JTAG interface and programming specific JTAG
instructions are given in the section
For more information about general Boundary-scan, the following literature can be consulted:
Bit
Read/Write
Initial Value
• Flash programming and verifying.
• EEPROM programming and verifying.
• Fuse programming and verifying.
• Lock bit programming and verifying.
• IEEE: IEEE Std. 1149.1-1990. IEEE Standard Test Access Port and Boundary-scan
• Colin Maunder: The Board Designers Guide to Testable Logic Circuits, Addison-Wesley,
Architecture, IEEE, 1993.
1992.
7
MSB/IDRD
R/W
0
6
R/W
0
5
R/W
0
“Programming via the JTAG Interface” on page
4
R/W
0
3
R/W
0
R/W
2
0
1
R/W
0
AT90USB64/128
0
LSB
R/W
0
OCDR
385.
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