AT90USB647-MU Atmel, AT90USB647-MU Datasheet - Page 201

• Manufacturer Part Number: AT90USB647-MU
• Description: MCU, 8BIT, 64K FLASH, USB, 64QFN
• Manufacturer: Atmel

Specifications of AT90USB647-MU

• Controller Family/series: AT90
• No. Of I/o's: 48
• Eeprom Memory Size: 2KB
• Ram Memory Size: 4KB
• Cpu Speed: 16MHz
• No. Of: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 64KB
• Oscillator Type: External, Internal
• Package: 64QFN EP
• Device Core: AVR
• Family Name: AT90
• Maximum Speed: 20 MHz
• Ram Size: 4 KB
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 48
• Interface Type: SPI/TWI/USART/USB
• On-chip Adc: 8-chx10-bit
• Operating Temperature: -40 to 85 °C
• Number Of Timers: 4
• Lead Free Status / Rohs Status: Details

18.9.4
7593K–AVR–11/09
USART Control and Status Register n C – UCSRnC
zero) will not become effective until ongoing and pending transmissions are completed, i.e.,
when the Transmit Shift Register and Transmit Buffer Register do not contain data to be trans-
mitted. When disabled, the Transmitter will no longer override the TxDn port.
• Bit 2 – UCSZn2: Character Size n
The UCSZn2 bits combined with the UCSZn1:0 bit in UCSRnC sets the number of data bits
(Character SiZe) in a frame the Receiver and Transmitter use.
• Bit 1 – RXB8n: Receive Data Bit 8 n
RXB8n is the ninth data bit of the received character when operating with serial frames with nine
data bits. Must be read before reading the low bits from UDRn.
• Bit 0 – TXB8n: Transmit Data Bit 8 n
TXB8n is the ninth data bit in the character to be transmitted when operating with serial frames
with nine data bits. Must be written before writing the low bits to UDRn.
• Bits 7:6 – UMSELn1:0 USART Mode Select
These bits select the mode of operation of the USARTn as shown in
Table 18-4.
Note:
• Bits 5:4 – UPMn1:0: Parity Mode
These bits enable and set type of parity generation and check. If enabled, the Transmitter will
automatically generate and send the parity of the transmitted data bits within each frame. The
Receiver will generate a parity value for the incoming data and compare it to the UPMn setting.
If a mismatch is detected, the UPEn Flag in UCSRnA will be set.
Table 18-5.
Bit
Read/Write
Initial Value
UMSELn1
UPMn1
1. See
0
0
1
1
0
0
1
1
operation
7
UMSELn1
R/W
0
UMSELn Bits Settings
UPMn Bits Settings
“USART in SPI Mode” on page 206
6
UMSELn0
R/W
0
UMSELn0
UPMn0
0
1
0
1
0
1
0
1
UPMn1
R/W
5
0
Parity Mode
Disabled
Reserved
Enabled, Even Parity
Enabled, Odd Parity
UPMn0
R/W
4
0
Mode
Asynchronous USART
Synchronous USART
(Reserved)
Master SPI (MSPIM)
3
USBSn
R/W
0
for full description of the Master SPI Mode (MSPIM)
2
UCSZn1
R/W
1
(1)
1
UCSZn0
R/W
1
AT90USB64/128
Table
0
UCPOLn
R/W
0
18-4..
UCSRnC
201