AT90USB647-MU Atmel, AT90USB647-MU Datasheet - Page 340

• Manufacturer Part Number: AT90USB647-MU
• Description: MCU, 8BIT, 64K FLASH, USB, 64QFN
• Manufacturer: Atmel

Specifications of AT90USB647-MU

• Controller Family/series: AT90
• No. Of I/o's: 48
• Eeprom Memory Size: 2KB
• Ram Memory Size: 4KB
• Cpu Speed: 16MHz
• No. Of: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 64KB
• Oscillator Type: External, Internal
• Package: 64QFN EP
• Device Core: AVR
• Family Name: AT90
• Maximum Speed: 20 MHz
• Ram Size: 4 KB
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 48
• Interface Type: SPI/TWI/USART/USB
• On-chip Adc: 8-chx10-bit
• Operating Temperature: -40 to 85 °C
• Number Of Timers: 4
• Lead Free Status / Rohs Status: Details

27.3.4
27.4
27.4.1
27.4.2
340
Boundary-scan Specific JTAG Instructions
AT90USB64/128
Boundary-scan Chain
EXTEST; 0x0
IDCODE; 0x1
Figure 27-2. Reset Register
The Boundary-scan Chain has the capability of driving and observing the logic levels on the dig-
ital I/O pins, as well as the boundary between digital and analog logic for analog circuitry having
off-chip connections.
See
The Instruction Register is 4-bit wide, supporting up to 16 instructions. Listed below are the
JTAG instructions useful for Boundary-scan operation. Note that the optional HIGHZ instruction
is not implemented, but all outputs with tri-state capability can be set in high-impedant state by
using the AVR_RESET instruction, since the initial state for all port pins is tri-state.
As a definition in this datasheet, the LSB is shifted in and out first for all Shift Registers.
The OPCODE for each instruction is shown behind the instruction name in hex format. The text
describes which Data Register is selected as path between TDI and TDO for each instruction.
Mandatory JTAG instruction for selecting the Boundary-scan Chain as Data Register for testing
circuitry external to the AVR package. For port-pins, Pull-up Disable, Output Control, Output
Data, and Input Data are all accessible in the scan chain. For Analog circuits having off-chip
connections, the interface between the analog and the digital logic is in the scan chain. The con-
tents of the latched outputs of the Boundary-scan chain is driven out as soon as the JTAG IR-
Register is loaded with the EXTEST instruction.
The active states are:
Optional JTAG instruction selecting the 32 bit ID-Register as Data Register. The ID-Register
consists of a version number, a device number and the manufacturer code chosen by JEDEC.
This is the default instruction after power-up.
• Capture-DR: Data on the external pins are sampled into the Boundary-scan Chain.
• Shift-DR: The Internal Scan Chain is shifted by the TCK input.
• Update-DR: Data from the scan chain is applied to output pins.
“Boundary-scan Chain” on page 342
From Other Internal and
External Reset Sources
From
ClockDR · AVR_RESET
TDI
D
for a complete description.
Q
TDO
To
Internal reset
7593K–AVR–11/09