AT90USB647-MU Atmel, AT90USB647-MU Datasheet - Page 307
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AT90USB647-MU
Manufacturer Part Number
AT90USB647-MU
Description
MCU, 8BIT, 64K FLASH, USB, 64QFN
Manufacturer
Atmel
Specifications of AT90USB647-MU
Controller Family/series
AT90
No. Of I/o's
48
Eeprom Memory Size
2KB
Ram Memory Size
4KB
Cpu Speed
16MHz
No. Of
RoHS Compliant
Core Size
8bit
Program Memory Size
64KB
Oscillator Type
External, Internal
Package
64QFN EP
Device Core
AVR
Family Name
AT90
Maximum Speed
20 MHz
Ram Size
4 KB
Operating Supply Voltage
3.3|5 V
Data Bus Width
8 Bit
Program Memory Type
Flash
Number Of Programmable I/os
48
Interface Type
SPI/TWI/USART/USB
On-chip Adc
8-chx10-bit
Operating Temperature
-40 to 85 °C
Number Of Timers
4
Lead Free Status / Rohs Status
Details
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AT90USB64/128
Set by hardware when a NAK has been received on the current bank of the Pipe. This triggers
an interrupt if the NAKEDE bit is set in the UPIENX register.
Shall be clear to handshake the interrupt. Setting by software has no effect.
• 5 - RWAL - Read/Write Allowed
OUT Pipe:
Set by hardware when the firmware can write a new data into the Pipe FIFO.
Cleared by hardware when the current Pipe FIFO is full.
IN Pipe:
Set by hardware when the firmware can read a new data into the Pipe FIFO.
Cleared by hardware when the current Pipe FIFO is empty.
This bit is also cleared by hardware when the RXSTALL or the PERR bit is set
• 4 - PERRI -PIPE Error
Set by hardware when an error occurs on the current bank of the Pipe. This triggers an interrupt
if the PERRE bit is set in the UPIENX register. Refers to the UPERRX register to determine the
source of the error.
Automatically cleared by hardware when the error source bit is cleared.
• 3 - TXSTPI - SETUP Bank ready
Set by hardware when the current SETUP bank is free and can be filled. This triggers an inter-
rupt if the TXSTPE bit is set in the UPIENX register.
Shall be cleared to handshake the interrupt. Setting by software has no effect.
• 2 - TXOUTI -OUT Bank ready
Set by hardware when the current OUT bank is free and can be filled. This triggers an interrupt if
the TXOUTE bit is set in the UPIENX register.
Shall be cleared to handshake the interrupt. Setting by software has no effect.
• 1 - RXSTALLI / CRCERR - STALL Received / Isochronous CRC Error
Set by hardware when a STALL handshake has been received on the current bank of the Pipe.
The Pipe is automatically frozen. This triggers an interrupt if the RXSTALLE bit is set in the UPI-
ENX register.
Shall be cleared to handshake the interrupt. Setting by software has no effect.
For Isochronous Pipe:
Set by hardware when a CRC error occurs on the current bank of the Pipe. This triggers an inter-
rupt if the TXSTPE bit is set in the UPIENX register.
Shall be cleared to handshake the interrupt. Setting by software has no effect.
• 0 - RXINI - IN Data received
Set by hardware when a new USB message is stored in the current bank of the Pipe. This trig-
gers an interrupt if the RXINE bit is set in the UPIENX register.
Shall be cleared to handshake the interrupt. Setting by software has no effect.
307
7593K–AVR–11/09
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