AT90USB647-MU Atmel, AT90USB647-MU Datasheet - Page 341
AT90USB647-MU
Manufacturer Part Number
AT90USB647-MU
Description
MCU, 8BIT, 64K FLASH, USB, 64QFN
Manufacturer
Atmel
Specifications of AT90USB647-MU
Controller Family/series
AT90
No. Of I/o's
48
Eeprom Memory Size
2KB
Ram Memory Size
4KB
Cpu Speed
16MHz
No. Of
RoHS Compliant
Core Size
8bit
Program Memory Size
64KB
Oscillator Type
External, Internal
Package
64QFN EP
Device Core
AVR
Family Name
AT90
Maximum Speed
20 MHz
Ram Size
4 KB
Operating Supply Voltage
3.3|5 V
Data Bus Width
8 Bit
Program Memory Type
Flash
Number Of Programmable I/os
48
Interface Type
SPI/TWI/USART/USB
On-chip Adc
8-chx10-bit
Operating Temperature
-40 to 85 °C
Number Of Timers
4
Lead Free Status / Rohs Status
Details
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27.4.3
27.4.4
27.4.5
27.5
27.5.1
7593K–AVR–11/09
Boundary-scan Related Register in I/O Memory
SAMPLE_PRELOAD; 0x2
AVR_RESET; 0xC
BYPASS; 0xF
MCU Control Register – MCUCR
The active states are:
Mandatory JTAG instruction for pre-loading the output latches and taking a snap-shot of the
input/output pins without affecting the system operation. However, the output latches are not
connected to the pins. The Boundary-scan Chain is selected as Data Register.
The active states are:
The AVR specific public JTAG instruction for forcing the AVR device into the Reset mode or
releasing the JTAG reset source. The TAP controller is not reset by this instruction. The one bit
Reset Register is selected as Data Register. Note that the reset will be active as long as there is
a logic “one” in the Reset Chain. The output from this chain is not latched.
The active states are:
Mandatory JTAG instruction selecting the Bypass Register for Data Register.
The active states are:
The MCU Control Register contains control bits for general MCU functions.
• Bits 7 – JTD: JTAG Interface Disable
When this bit is zero, the JTAG interface is enabled if the JTAGEN Fuse is programmed. If this
bit is one, the JTAG interface is disabled. In order to avoid unintentional disabling or enabling of
the JTAG interface, a timed sequence must be followed when changing this bit: The application
software must write this bit to the desired value twice within four cycles to change its value. Note
that this bit must not be altered when using the On-chip Debug system.
Bit
Read/Write
Initial Value
• Capture-DR: Data in the IDCODE Register is sampled into the Boundary-scan Chain.
• Shift-DR: The IDCODE scan chain is shifted by the TCK input.
• Capture-DR: Data on the external pins are sampled into the Boundary-scan Chain.
• Shift-DR: The Boundary-scan Chain is shifted by the TCK input.
• Update-DR: Data from the Boundary-scan chain is applied to the output latches. However,
• Shift-DR: The Reset Register is shifted by the TCK input.
• Capture-DR: Loads a logic “0” into the Bypass Register.
• Shift-DR: The Bypass Register cell between TDI and TDO is shifted.
the output latches are not connected to the pins.
7
JTD
R/W
0
6
–
R
0
5
–
R
0
4
PUD
R/W
0
3
–
R
0
2
–
R
0
1
IVSEL
R/W
0
AT90USB64/128
0
IVCE
R/W
0
MCUCR
341
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