AT90USB647-MU Atmel, AT90USB647-MU Datasheet - Page 15

• Manufacturer Part Number: AT90USB647-MU
• Description: MCU, 8BIT, 64K FLASH, USB, 64QFN
• Manufacturer: Atmel

Specifications of AT90USB647-MU

• Controller Family/series: AT90
• No. Of I/o's: 48
• Eeprom Memory Size: 2KB
• Ram Memory Size: 4KB
• Cpu Speed: 16MHz
• No. Of: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 64KB
• Oscillator Type: External, Internal
• Package: 64QFN EP
• Device Core: AVR
• Family Name: AT90
• Maximum Speed: 20 MHz
• Ram Size: 4 KB
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 48
• Interface Type: SPI/TWI/USART/USB
• On-chip Adc: 8-chx10-bit
• Operating Temperature: -40 to 85 °C
• Number Of Timers: 4
• Lead Free Status / Rohs Status: Details

4.6.1
4.7
7593K–AVR–11/09
Instruction Execution Timing
Extended Z-pointer Register for ELPM/SPM - RAMPZ
For ELPM/SPM instructions, the Z-pointer is a concatenation of RAMPZ, ZH, and ZL, as shown
in Figure 4-4. Note that LPM is not affected by the RAMPZ setting.
Figure 4-4.
The actual number of bits is implementation dependent. Unused bits in an implementation will
always read as zero. For compatibility with future devices, be sure to write these bits to zero.
This section describes the general access timing concepts for instruction execution. The AVR
CPU is driven by the CPU clock clk
chip. No internal clock division is used.
Figure 4-5
vard architecture and the fast-access Register File concept. This is the basic pipelining concept
to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost,
functions per clocks, and functions per power-unit.
Figure 4-5.
Figure 4-6
operation using two register operands is executed, and the result is stored back to the destina-
tion register.
Bit
Read/Write
Initial Value
Bit (
Individually)
Bit (Z-pointer)
2nd Instruction Execute
3rd Instruction Execute
1st Instruction Execute
2nd Instruction Fetch
3rd Instruction Fetch
4th Instruction Fetch
1st Instruction Fetch
shows the internal timing concept for the Register File. In a single clock cycle an ALU
shows the parallel instruction fetches and instruction executions enabled by the Har-
The Z-pointer used by ELPM and SPM
The Parallel Instruction Fetches and Instruction Executions
7
RAMPZ
7
R/W
0
7
RAMPZ
23
clk
CPU
6
RAMPZ
6
R/W
0
5
RAMPZ
5
R/W
0
0
16
CPU
T1
, directly generated from the selected clock source for the
4
RAMPZ
4
R/W
0
7
ZH
15
3
RAMPZ
3
R/W
0
T2
2
RAMPZ
2
R/W
0
0
8
AT90USB64/128
T3
1
RAMPZ1
0
R/W
7
ZL
7
0
RAMPZ0
R/W
0
T4
RAMPZ
0
0
15