LPC1764FBD100 NXP Semiconductors, LPC1764FBD100 Datasheet - Page 28

• Manufacturer Part Number: LPC1764FBD100
• Description: IC, 32BIT MCU ARM CORTEX 100MHZ LQFP-100
• Manufacturer: NXP Semiconductors

Specifications of LPC1764FBD100

• Controller Family/series: (ARM Cortex)
• No. Of I/o's: 70
• Ram Memory Size: 32KB
• Cpu Speed: 100MHz
• No. Of Timers: 4
• Interface: CAN, I2C, SPI, UART
• Core Size: 32 Bit
• Program Memory Size: 128KB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
LPC1768_66_65_64_2
Objective data sheet
7.25.1 Features
7.27.1 Features
7.25 Repetitive Interrupt (RI) timer
7.26 System tick timer
7.27 Watchdog timer
The repetitive interrupt timer provides a free-running 32-bit counter which is compared to
a selectable value, generating an interrupt when a match occurs. Any bits of the
timer/compare can be masked such that they do not contribute to the match detection.
The repetitive interrupt timer can be used to create an interrupt that repeats at
predetermined intervals.
The ARM Cortex-M3 includes a system tick timer (SYSTICK) that is intended to generate
a dedicated SYSTICK exception at a 10 ms interval. In the LPC1768/66/65/64, this timer
can be clocked from the internal AHB clock or from a device pin.
The purpose of the watchdog is to reset the microcontroller within a reasonable amount of
time if it enters an erroneous state. When enabled, the watchdog will generate a system
reset if the user program fails to ‘feed’ (or reload) the watchdog within a predetermined
amount of time.
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32-bit counter running from PCLK. Counter can be free-running or be reset by a
generated interrupt.
32-bit compare value.
32-bit compare mask. An interrupt is generated when the counter value equals the
compare value, after masking. This allows for combinations not possible with a simple
compare.
Internally resets chip if not periodically reloaded.
Debug mode.
Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be
disabled.
Incorrect/Incomplete feed sequence causes reset/interrupt if enabled.
Flag to indicate watchdog reset.
Programmable 32-bit timer with internal prescaler.
Selectable time period from (T
multiples of T
The Watchdog Clock (WDCLK) source can be selected from the Internal RC (IRC)
oscillator or the APB peripheral clock. This gives a wide range of potential timing
choices of Watchdog operation under different power reduction conditions. It also
provides the ability to run the WDT from an entirely internal source that is not
dependent on an external crystal and its associated components and wiring for
increased reliability.
Includes lock/safe feature.
cy(WDCLK)
Rev. 02 — 11 February 2009
4.
cy(WDCLK)
256
32-bit ARM Cortex-M3 microcontroller
LPC1768/66/65/64
4) to (T
cy(WDCLK)
© NXP B.V. 2009. All rights reserved.
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