LPC1764FBD100 NXP Semiconductors, LPC1764FBD100 Datasheet - Page 14

• Manufacturer Part Number: LPC1764FBD100
• Description: IC, 32BIT MCU ARM CORTEX 100MHZ LQFP-100
• Manufacturer: NXP Semiconductors

Specifications of LPC1764FBD100

• Controller Family/series: (ARM Cortex)
• No. Of I/o's: 70
• Ram Memory Size: 32KB
• Cpu Speed: 100MHz
• No. Of Timers: 4
• Interface: CAN, I2C, SPI, UART
• Core Size: 32 Bit
• Program Memory Size: 128KB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
Table 3.
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
7. Functional description
LPC1768_66_65_64_2
Objective data sheet
Symbol
V
VREFP
VREFN
VBAT
n.c.
DDA
5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis.
5 V tolerant pad providing digital I/O functions (with TTL levels and hysteresis) and analog input. When configured as a ADC input,
digital section of the pad is disabled.
5 V tolerant pad providing digital I/O with TTL levels and hysteresis and analog output function. When configured as the DAC output,
digital section of the pad is disabled.
Open-drain 5 V tolerant digital I/O pad, compatible with I
output functionality. When power is switched off, this pin connected to the I
Open-drain configuration applies to all functions on this pin.
Pad provides digital I/O and USB functions. It is designed in accordance with the USB specification, revision 2.0 (Full-speed and
Low-speed mode only).
5 V tolerant pad with 5 ns glitch filter providing digital I/O functions with TTL levels and hysteresis.
5 V tolerant pad with 20 ns glitch filter providing digital I/O function with TTL levels and hysteresis.
Pad provides special analog functionality.
Pin description
7.1 Architectural overview
7.2 ARM Cortex-M3 processor
Pin
10
12
15
19
13
[8]
[8]
[8]
The ARM Cortex-M3 includes three AHB-Lite buses: the system bus, the I-code bus, and
the D-code bus (see
system bus and are used similarly to TCM interfaces: one bus dedicated for instruction
fetch (I-code) and one bus for data access (D-code). The use of two core buses allows for
simultaneous operations if concurrent operations target different devices.
The LPC1768/66/65/64 use a multi-layer AHB matrix to connect the ARM Cortex-M3
buses and other bus masters to peripherals in a flexible manner that optimizes
performance by allowing peripherals that are on different slaves ports of the matrix to be
accessed simultaneously by different bus masters.
The ARM Cortex-M3 is a general purpose, 32-bit microprocessor, which offers high
performance and very low power consumption. The ARM Cortex-M3 offers many new
features, including a Thumb-2 instruction set, low interrupt latency, hardware divide,
interruptable/continuable multiple load and store instructions, automatic state save and
restore for interrupts, tightly integrated interrupt controller with wakeup interrupt controller,
and multiple core buses capable of simultaneous accesses.
…continued
Type
I
I
I
I
-
Description
analog 3.3 V pad supply voltage: This should be nominally the same voltage as
V
power the ADC and DAC.
ADC positive reference voltage: This should be nominally the same voltage as
V
as a reference for ADC and DAC.
ADC negative reference voltage: This should be nominally the same voltage as
V
a reference for ADC and DAC.
RTC pin power supply: 3.3 V on this pin supplies the power to the RTC
peripheral.
not connected
DD(3V3)
DDA
SS
but should be isolated to minimize noise and error. Level on this pin is used as
but should be isolated to minimize noise and error. Level on this pin is used
Figure
Rev. 02 — 11 February 2009
but should be isolated to minimize noise and error. This voltage is used to
2
C-bus 400 kHz specification. This pad requires an external pull-up to provide
1). The I-code and D-code core buses are faster than the
2
C-bus is floating and does not disturb the I
32-bit ARM Cortex-M3 microcontroller
LPC1768/66/65/64
© NXP B.V. 2009. All rights reserved.
2
C lines.
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