LPC1764FBD100 NXP Semiconductors, LPC1764FBD100 Datasheet - Page 24

• Manufacturer Part Number: LPC1764FBD100
• Description: IC, 32BIT MCU ARM CORTEX 100MHZ LQFP-100
• Manufacturer: NXP Semiconductors

Specifications of LPC1764FBD100

• Controller Family/series: (ARM Cortex)
• No. Of I/o's: 70
• Ram Memory Size: 32KB
• Cpu Speed: 100MHz
• No. Of Timers: 4
• Interface: CAN, I2C, SPI, UART
• Core Size: 32 Bit
• Program Memory Size: 128KB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
LPC1768_66_65_64_2
Objective data sheet
7.18.1 Features
7.19.1 Features
7.19 I
7.20 I
The LPC1768/66/65/64 each contain three I
The I
(SCL) and a Serial Data Line (SDA). Each device is recognized by a unique address and
can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the
capability to both receive and send information (such as memory). Transmitters and/or
receivers can operate in either master or slave mode, depending on whether the chip has
to initiate a data transfer or is only addressed. The I
controlled by more than one bus master connected to it.
Remark: The I
The I
2
2
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C-bus serial I/O controllers
S-bus serial I/O controllers
Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National
Semiconductor Microwire buses
Synchronous serial communication
Master or slave operation
8-frame FIFOs for both transmit and receive
4-bit to 16-bit frame
DMA transfers supported by GPDMA
I
supports Fast mode plus with bit rates up to 1 Mbit/s.
I
Easy to configure as master, slave, or master/slave.
Programmable clocks allow versatile rate control.
Bidirectional data transfer between masters and slaves.
Multi-master bus (no central master).
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus.
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
The I
All I
2
2
2
2
C0 is a standard I
C1 and I
C-bus is bidirectional for inter-IC control using only two wires: a Serial Clock line
S-bus provides a standard communication interface for digital audio applications.
2
C-bus controllers support multiple address recognition and a bus monitor mode.
2
C-bus can be used for test and diagnostic purposes.
2
2
C2 use standard I/O pins with bit rates of up to 400 kbit/s (Fast I
S-bus is not available on the LPC1764.
Rev. 02 — 11 February 2009
2
C compliant bus interface with open-drain pins. I
2
C-bus controllers.
32-bit ARM Cortex-M3 microcontroller
LPC1768/66/65/64
2
C is a multi-master bus and can be
© NXP B.V. 2009. All rights reserved.
2
C0 also
2
C-bus).
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