LPC1764FBD100 NXP Semiconductors, LPC1764FBD100 Datasheet - Page 25

• Manufacturer Part Number: LPC1764FBD100
• Description: IC, 32BIT MCU ARM CORTEX 100MHZ LQFP-100
• Manufacturer: NXP Semiconductors

Specifications of LPC1764FBD100

• Controller Family/series: (ARM Cortex)
• No. Of I/o's: 70
• Ram Memory Size: 32KB
• Cpu Speed: 100MHz
• No. Of Timers: 4
• Interface: CAN, I2C, SPI, UART
• Core Size: 32 Bit
• Program Memory Size: 128KB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
LPC1768_66_65_64_2
Objective data sheet
7.20.1 Features
7.21.1 Features
7.21 General purpose 32-bit timers/external event counters
The I
and one word select signal. The basic I
always the master, and one slave. The I
separate transmit and receive channel, each of which can operate as either a master or a
slave.
The LPC1768/66/65/64 include four 32-bit timer/counters. The timer/counter is designed
to count cycles of the system derived clock or an externally-supplied clock. It can
optionally generate interrupts, generate timed DMA requests, or perform other actions at
specified timer values, based on four match registers. Each timer/counter also includes
two capture inputs to trap the timer value when an input signal transitions, optionally
generating an interrupt.
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The interface has separate input/output channels each of which can operate in master
or slave mode.
Capable of handling 8-bit, 16-bit, and 32-bit word sizes.
Mono and stereo audio data supported.
The sampling frequency can range from 16 kHz to 96 kHz (16, 22.05, 32, 44.1, 48,
96) kHz.
Support for an audio master clock.
Configurable word select period in master mode (separately for I
output).
Two 8-word FIFO data buffers are provided, one for transmit and one for receive.
Generates interrupt requests when buffer levels cross a programmable boundary.
Two DMA requests, controlled by programmable buffer levels. These are connected to
the GPDMA block.
Controls include reset, stop and mute options separately for I
output.
A 32-bit timer/counter with a programmable 32-bit prescaler.
Counter or timer operation.
Two 32-bit capture channels per timer, that can take a snapshot of the timer value
when an input signal transitions. A capture event may also generate an interrupt.
Four 32-bit match registers that allow:
– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.
Up to four external outputs corresponding to match registers, with the following
capabilities:
– Set LOW on match.
– Set HIGH on match.
2
S-bus specification defines a 3-wire serial bus using one data line, one clock line,
Rev. 02 — 11 February 2009
2
2
S-bus connection has one master, which is
S-bus interface on the LPC1768/66/65 provides a
32-bit ARM Cortex-M3 microcontroller
LPC1768/66/65/64
2
S-bus input and I
2
S-bus input and
© NXP B.V. 2009. All rights reserved.
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S-bus