LPC1764FBD100 NXP Semiconductors, LPC1764FBD100 Datasheet - Page 23

• Manufacturer Part Number: LPC1764FBD100
• Description: IC, 32BIT MCU ARM CORTEX 100MHZ LQFP-100
• Manufacturer: NXP Semiconductors

Specifications of LPC1764FBD100

• Controller Family/series: (ARM Cortex)
• No. Of I/o's: 70
• Ram Memory Size: 32KB
• Cpu Speed: 100MHz
• No. Of Timers: 4
• Interface: CAN, I2C, SPI, UART
• Core Size: 32 Bit
• Program Memory Size: 128KB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
LPC1768_66_65_64_2
Objective data sheet
7.16.1 Features
7.17.1 Features
7.16 UARTs
7.17 SPI serial I/O controller
7.18 SSP serial I/O controller
The LPC1768/66/65/64 each contain four UARTs. In addition to standard transmit and
receive data lines, UART1 also provides a full modem control handshake interface.
Support for RS-485/9-bit mode allows both software address detection and automatic
address detection using 9-bit mode.
The UARTs include a fractional baud rate generator. Standard baud rates such as
115200 Bd can be achieved with any crystal frequency above 2 MHz.
The LPC1768/66/65/64 contain one SPI controller. SPI is a full duplex serial interface
designed to handle multiple masters and slaves connected to a given bus. Only a single
master and a single slave can communicate on the interface during a given data transfer.
During a data transfer the master always sends 8 bits to 16 bits of data to the slave, and
the slave always sends 8 bits to 16 bits of data to the master.
The LPC1768/66/65/64 contain two SSP controllers. The SSP controller is capable of
operation on a SPI, 4-wire SSI, or Microwire bus. It can interact with multiple masters and
slaves on the bus. Only a single master and a single slave can communicate on the bus
during a given data transfer. The SSP supports full duplex transfers, with frames of 4 bits
to 16 bits of data flowing from the master to the slave and from the slave to the master. In
practice, often only one of these data flows carries meaningful data.
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16 B Receive and Transmit FIFOs.
Register locations conform to 16C550 industry standard.
Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.
Built-in fractional baud rate generator covering wide range of baud rates without a
need for external crystals of particular values.
Fractional divider for baud rate control, auto baud capabilities and FIFO control
mechanism that enables software flow control implementation.
UART1 equipped with standard modem interface signals. This module also provides
full support for hardware flow control (auto-CTS/RTS).
Support for RS-485/9-bit mode.
UART3 includes an IrDA mode to support infrared communication.
All UARTs have DMA support.
Compliant with SPI specification
Synchronous, serial, full duplex communication
Combined SPI master and slave
Maximum data bit rate of one eighth of the input clock rate
8 bits to 16 bits per transfer
Rev. 02 — 11 February 2009
32-bit ARM Cortex-M3 microcontroller
LPC1768/66/65/64
© NXP B.V. 2009. All rights reserved.
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