LPC1764FBD100 NXP Semiconductors, LPC1764FBD100 Datasheet - Page 2

• Manufacturer Part Number: LPC1764FBD100
• Description: IC, 32BIT MCU ARM CORTEX 100MHZ LQFP-100
• Manufacturer: NXP Semiconductors

Specifications of LPC1764FBD100

• Controller Family/series: (ARM Cortex)
• No. Of I/o's: 70
• Ram Memory Size: 32KB
• Cpu Speed: 100MHz
• No. Of Timers: 4
• Interface: CAN, I2C, SPI, UART
• Core Size: 32 Bit
• Program Memory Size: 128KB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
LPC1768_66_65_64_2
Objective data sheet
I
I
I
I
I
Eight channel General Purpose DMA controller (GPDMA) on the AHB multilayer
matrix that can be used with the SSP, I
Digital-to-Analog converter peripherals, timer match signals, and for
memory-to-memory transfers.
Multilayer AHB matrix interconnect provides a separate bus for each AHB master. AHB
masters include the CPU, General Purpose DMA controller, Ethernet MAC
(LPC1768/66/64 only), and the USB interface. This interconnect provides
communication with no arbitration delays.
Split APB bus allows high throughput with few stalls between the CPU and DMA.
Serial interfaces:
Other peripherals:
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
Ethernet MAC with RMII interface and dedicated DMA controller (LPC1768/66/64
only).
USB 2.0 full-speed device/Host/OTG controller with dedicated DMA controller and
on-chip PHY for device, Host, and OTG functions. The LPC1764 includes a device
controller only.
Four UARTs with fractional baud rate generation, internal FIFO, DMA support, and
RS-485 support. One UART has modem control I/O, and one UART has IrDA
support.
CAN 2.0B controller with two channels.
SPI controller with synchronous, serial, full duplex communication and
programmable data length.
Two SSP controllers with FIFO and multi-protocol capabilities. The SSP interfaces
can be used with the GPDMA controller.
Two I
multiple address recognition and monitor mode.
One I
a data rate of 1 Mbit/s with multiple address recognition and monitor mode.
On the LPC1768/66/65 only, I
output, with fractional rate control. The I
GPDMA. The I
receive as well as master clock input/output.
70 General Purpose I/O (GPIO) pins with configurable pull-up/down resistors and a
new, configurable open-drain operating mode.
12-bit Analog-to-Digital Converter (ADC) with input multiplexing among eight pins,
conversion rates up to 1 MHz, and multiple result registers. The 12-bit ADC can be
used with the GPDMA controller.
10-bit Digital-to-Analog Converter (DAC) with dedicated conversion timer and DMA
support (LPC1768/66/65 only).
Four general purpose timers/counters, with a total of eight capture inputs and ten
compare outputs. Each timer block has an external count input and DMA support.
One motor control PWM with support for three-phase motor control.
Quadrature encoder interface that can monitor one external quadrature encoder.
One standard PWM/timer block with external count input.
RTC with a separate power domain and dedicated RTC oscillator. The RTC block
includes 64 bytes of battery-powered backup registers.
Watchdog Timer (WDT) resets the microcontroller within a reasonable amount of
time if it enters an erroneous state.
2
2
C-bus interfaces supporting fast mode with a data rate of 400 kbits/s with
C-bus interface supporting full I
2
Rev. 02 — 11 February 2009
S-bus interface supports 3-wire and 4-wire data transmit and
2
S (Inter-IC Sound) interface for digital audio input or
2
S-bus, UART, the Analog-to-Digital and
2
C-bus specification and fast mode plus with
2
S-bus interface can be used with the
32-bit ARM Cortex-M3 microcontroller
LPC1768/66/65/64
© NXP B.V. 2009. All rights reserved.
2 of 72