ADSP-BF538BBCZ-5F4 Analog Devices Inc, ADSP-BF538BBCZ-5F4 Datasheet - Page 38

• Manufacturer Part Number: ADSP-BF538BBCZ-5F4
• Description: IC, FLOAT-PT DSP, 16BIT, 533MHZ, BGA-316
• Manufacturer: Analog Devices Inc
• Series: Blackfinr
• Type: Fixed Pointr

Specifications of ADSP-BF538BBCZ-5F4

• No. Of Bits: 16 Bit
• Frequency: 533MHz
• Supply Voltage: 1.25V
• Embedded Interface Type: CAN, I2C, PPI, SPI, TWI, UART
• No. Of I/o's: 54
• Flash Memory Size: 512KB
• Interface: CAN, SPI, SSP, TWI, UART
• Clock Rate: 533MHz
• Non-volatile Memory: FLASH (512 kB)
• On-chip Ram: 148kB
• Voltage - I/o: 3.00V, 3.30V
• Voltage - Core: 1.25V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 316-CSPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: ADZS-BFAUDIO-EZEXT - BOARD EVAL AUDIO BLACKFIN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

ADSP-BF538/ADSP-BF538F
Serial Port Timing
Table 30
through
Table 31. Serial Ports—External Clock
1
2
3
Table 32. Serial Ports—Internal Clock
1
2
Parameter
Timing Requirements
t
t
t
t
t
t
t
t
Switching Characteristics
t
t
t
t
Parameter
Timing Requirements
t
t
t
t
Switching Characteristics
t
t
t
t
t
Referenced to sample edge.
Verified in design but untested. After being enabled, the serial port requires external clock pulses—before the first external frame sync edge—to initialize the serial port.
Referenced to drive edge.
Referenced to sample edge.
Referenced to drive edge.
SFSE
HFSE
SDRE
HDRE
SCLKEW
SCLKE
SUDTE
SUDRE
DFSE
HOFSE
DDTE
HDTE
SFSI
HFSI
SDRI
HDRI
DFSI
HOFSI
DDTI
HDTI
SCLKIW
Figure 26 on Page 41
through
Table 34 on Page 41
TFSx/RFSx Setup Before TSCLKx/RSCLKx (Externally Generated TFSx/RFSx)
TFSx/RFSx Hold After TSCLKx/RSCLKx (Externally Generated TFSx/RFSx)
Receive Data Setup Before RSCLKx
Receive Data Hold After RSCLKx
TSCLKx/RSCLKx Width
TSCLKx/RSCLKx Period
Start-Up Delay From SPORT Enable To First External TFSx
Start-Up Delay From SPORT Enable To First External RFSx
TFSx/RFSx Delay After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)
TFSx/RFSx Hold After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)
Transmit Data Delay After TSCLKx
Transmit Data Hold After TSCLKx
TFSx/RFSx Setup Before TSCLKx/RSCLKx (Externally Generated TFSx/RFSx)
TFSx/RFSx Hold After TSCLKx/RSCLKx (Externally Generated TFSx/RFSx)
Receive Data Setup Before RSCLKx
Receive Data Hold After RSCLKx
TFSx/RFSx Delay After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)
TFSx/RFSx Hold After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)
Transmit Data Delay After TSCLKx
Transmit Data Hold After TSCLKx
TSCLKx/RSCLKx Width
describe serial port operations.
and
Figure 23 on Page 39
1
1
3
2
3
2
Rev. D | Page 38 of 56 | July 2010
1
1
2
2
3
2
1
1
3
2
1
1
Min
3.0
3.0
3.0
3.0
4.5
15.0
4.0 × t
4.0 × t
0.0
0.0
Min
9.0
–1.5
9.0
–1.5
–1.0
–2.0
4.5
SCLKE
SCLKE
Max
10.0
10.0
Max
3.5
3.0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns