ADSP-BF538BBCZ-5F4 Analog Devices Inc, ADSP-BF538BBCZ-5F4 Datasheet
ADSP-BF538BBCZ-5F4
Specifications of ADSP-BF538BBCZ-5F4
Related parts for ADSP-BF538BBCZ-5F4
ADSP-BF538BBCZ-5F4 Summary of contents
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... EXTERNAL PORT FLASH, SDRAM CONTROL 16 8M BIT P ARALLEL FLASH (SEE TABLE 1) Figure 1. Functional Block Diagram One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 Embedded Processor ADSP-BF538/ADSP-BF538F 2 S channels 2 C industry standard INTERRUPT WATCHDOG CONTROLLER TIMER RTC ...
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... ADSP-BF538/ADSP-BF538F TABLE OF CONTENTS General Description ................................................. 3 Low Power Architecture ......................................... 3 System Integration ................................................ 3 ADSP-BF538/ADSP-BF538F Processor Peripherals ....... 3 Blackfin Processor Core .......................................... 4 Memory Architecture ............................................ 5 DMA Controllers .................................................. 8 Real-Time Clock ................................................... 9 Watchdog Timer .................................................. 9 Timers ............................................................... 9 Serial Ports (SPORTs) .......................................... 10 Serial Peripheral Interface (SPI) Ports ...................... 10 2-Wire Interface ................................................. 10 UART Ports ...................................................... 11 General-Purpose Ports ......................................... 11 Parallel Peripheral Interface ................................... 11 Controller Area Network (CAN) Interface ...
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... I/O pins. ADSP-BF538/ADSP-BF538F PROCESSOR ADSP-BF538F8 PERIPHERALS 4 The ADSP-BF538/ADSP-BF538F processors contain a rich set 3 of peripherals connected to the core via several high bandwidth 3 buses, providing flexibility in system configuration as well as excellent overall system performance (see the block diagram 1). ...
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... ADSP-BF538/ADSP-BF538F BLACKFIN PROCESSOR CORE As shown in Figure 2 on Page 4, the Blackfin processor core contains two 16-bit multipliers, two 40-bit accumulators, two 40-bit ALUs, four video ALUs, and a 40-bit shifter. The compu- tation units process 8-bit, 16-bit, or 32-bit data from the register file. ...
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... C/C++ compiler, resulting in fast and efficient software implementations. MEMORY ARCHITECTURE The ADSP-BF538/ADSP-BF538F processors view memory as a single unified 4G byte address space, using 32-bit addresses. All resources, including internal memory, external memory, and I/O control registers, occupy separate sections of this common address space ...
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... Figure 4 shows how the flash memory die and Blackfin proces- sor die are connected. The ADSP-BF538F8 contains an 8M bit (512K × 16-bit) bottom boot sector Spansion S29AL008J known good die flash memory. For additional information, visit www.spansion.com. Features include the following: • ...
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... The system interrupt controllers (SIC) provides the mapping and routing of events from the many peripheral interrupt sources to the prioritized general-purpose interrupt inputs of the CEC. Although the ADSP-BF538/ADSP-BF538F processors provide a default mapping, programs can alter the mappings and priorities of interrupt events by writing the appropriate val- ues into the interrupt assignment registers (SIC_IARx) ...
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... DMA CONTROLLERS The ADSP-BF538/ADSP-BF538F processors have two, inde- pendent DMA controllers that support automated data transfers with minimal overhead for the processor core. DMA transfers can occur between the processor internal memories and any of its DMA capable peripherals ...
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... DMA address within a common page In addition to the dedicated peripheral DMA channels, there are four memory DMA channels provided for transfers between the various memories of the ADSP-BF538/ADSP-BF538F proces- sor’s systems. This enables transfers of blocks of data between any of the memories—including external SDRAM, ROM, SRAM, and flash memory— ...
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... The serial clock line synchronizes the shifting and sam- pling of data on the two serial data lines. 2-WIRE INTERFACE The ADSP-BF538/ADSP-BF538F processors have two 2-wire interface (TWI) modules that are compatible with the Philips Inter-IC bus standard. The TWI modules offer the capabilities of simultaneous master and slave operation, support for 7-bit addressing and multimedia data arbitration ...
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... The capabilities of the UARTs are further extended with sup- port for the Infrared Data Association (IrDA Physical Layer Link Specification (SIR) protocol. GENERAL-PURPOSE PORTS The ADSP-BF538/ADSP-BF538F processors have gen- eral-purpose I/O pins that are multiplexed with other peripherals. They are arranged into Ports and F as shown in Table 4 ...
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... PPI_CONTROL register. Frame Capture Mode Frame capture mode allows the video source(s) to act as a slave (e.g., for frame capture). The ADSP-BF538/ADSP-BF538F pro- cessors control when to read from the video source(s). PPI_FS1 is an HSYNC output and PPI_FS2 is a VSYNC output. Output Mode Output mode is used for transmitting video or other data with up to three output frame syncs ...
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... DYNAMIC POWER MANAGEMENT The ADSP-BF538/ADSP-BF538F processors provide four oper- ating modes, each with a different performance/power profile. In addition, dynamic power management provides the control functions to dynamically alter the processor core supply voltage, further reducing power dissipation ...
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... Analog Devices website (www.analog.com)—use site search on “EE-228”. CLOCK SIGNALS ) × The ADSP-BF538/ADSP-BF538F processors can be clocked by 100% an external crystal, a sine wave input buffered, shaped clock derived from an external clock oscillator. for regula- Rev Page July 2010 SET OF DECOUPLING ...
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... This signal is connected to the processor’s CLKIN pin. When an external clock is used, the XTAL pin must be left unconnected. Alternatively, because the ADSP-BF538/ADSP-BF538F proces- sors include an on-chip oscillator circuit, an external crystal may be used. For fundamental frequency operation, use the cir- ...
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... Boot from 8-bit or 16-bit external flash memory – The 8-bit flash boot routine located in boot ROM memory space is set up using asynchronous memory bank 0. For ADSP-BF538F processors, the on-chip flash is booted if FCE is connected to AMS0. All configuration settings are set for the slowest device possible (3-cycle hold time; ...
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... File (LDF), allowing the developer to move between the graphi- cal and textual environments. Analog Devices emulators use the IEEE 1149.1 JTAG Test Access Port of the ADSP-BF538/ADSP-BF538F processors to monitor and control the target board processor during emula- tion. The emulator provides full speed emulation, allowing inspection and modification of memory, registers, and proces- sor stacks ...
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... RELATED DOCUMENTS ® evaluation plat- The following publications that describe the ADSP-BF538/ ADSP-BF538F processors (and related processors) can be ordered from any Analog Devices sales office or accessed elec- tronically on our website: • Getting Started with Blackfin Processors • ...
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... Output Enable Read Enable Write Enable Flash Enable (This pin is internally connected to GND on the ADSP-BF538.) Flash Reset (This pin is internally connected to GND on the ADSP-BF538.) Row Address Strobe Column Address Strobe Write Enable Clock Enable (This pin must be pulled low through a 10 kΩ resistor if hibernate state is used and SDRAM contents need to be preserved during hibernate ...
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... ADSP-BF538/ADSP-BF538F Table 10. Pin Descriptions (Continued) Pin Name I/O 2-Wire Interface Port SDA0 I SCL0 I SDA1 I SCL1 I Serial Port0 RSCLK0 I/O RFS0 I/O DR0PRI I DR0SEC I TSCLK0 I/O TFS0 I/O DT0PRI O DT0SEC O Serial Port1 RSCLK1 I/O RFS1 I/O DR1PRI I DR1SEC I TSCLK1 I/O TFS1 I/O ...
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... GPIO/SPI0 Slave Select Input GPIO/SPI0 Slave Select Enable 1/Timer Alternate Clock Input GPIO/SPI0 Slave Select Enable 2 GPIO/PPI Frame Sync 3/SPI0 Slave Select Enable 3 GPIO/PPI15/SPI0 Slave Select Enable 4 GPIO/PPI14/SPI0 Slave Select Enable 5 GPIO/PPI13/SPI0 Slave Select Enable 6 Rev Page July 2010 ADSP-BF538/ADSP-BF538F Driver Type ...
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... ADSP-BF538/ADSP-BF538F Table 10. Pin Descriptions (Continued) Pin Name I/O PF7/PPI12/SPI0SEL7 I/O PF8/PPI11 I/O PF9/PPI10 I/O PF10/PPI9 I/O PF11/PPI8 I/O PF12/PPI7 I/O PF13/PPI6 I/O PF14/PPI5 I/O PF15/PPI4 I/O Real-Time Clock RTXI I RTXO O JTAG Port TCK I TDO O TDI I TMS I TRST I EMU O Clock CLKIN I XTAL ...
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... AMBIENT The following bidirectional pins are 3.3 V tolerant: DATA15–0, SCK2–0, MISO2–0, MOSI2– The following bidirectional pins are 5 V tolerant: SCL0, SCL1, SDA0, SDA1, CANTX, CANRX, and IH Rev Page July 2010 ADSP-BF538/ADSP-BF538F Min Nom Max Unit 0.8 1.25 1 ...
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... ADSP-BF538/ADSP-BF538F The following tables describe the voltage/frequency require- ments for the ADSP-BF538/ADSP-BF538F processor clocks. Take care in selecting MSEL, SSEL, and CSEL ratios so as not to exceed the maximum core clock (Table 11 system clock (Table 14) specifications. Table 13 phase-locked loop operating conditions. Table 11. Core Clock (CCLK) Requirements - 400 MHz Models ...
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... Applies to three-statable pins. 6 Applies to all signal pins. 7 Guaranteed, but not tested. 8 See the ADSP-BF538/538F Blackfin Processor Hardware Reference for definitions of sleep, deep sleep, and hibernate operating modes. 9 See Table 16 for the list of I power vectors covered by various Activity Scaling Factors (ASF). ...
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... ADSP-BF538/ADSP-BF538F 1 Table 15. Static Current (mA) V (V) DDINT T (°C) 0.80 V 0. -40 6.4 7.7 8.8 -25 9.2 10.9 12.5 0 16.8 18.9 21.5 25 32.9 37.2 41.4 40 48.4 54.8 60.5 55 71.2 78.6 86.5 70 102.3 112.2 122.1 85 140.7 153.0 167.0 100 190.6 207.1 224.6 105 210.2 228.1 245 ...
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... Rev Page July 2010 ADSP-BF538/ADSP-BF538F Figure 9 and Table 20 provides Ordering Guide on Page 56. ADSP-BF538 tppZccc vvvvvv.x n.n yyww country_of_origin Figure 9. Product Information on Package Field Description Temperature Range Package Type RoHS Compliant Part See Ordering Guide Assembly Lot Code Silicon Revision ...
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... ADSP-BF538/ADSP-BF538F TIMING SPECIFICATIONS Component specifications are subject to change with PCN notice. Clock and Reset Timing Table 21 and Figure 10 describe clock and reset operations. Per Absolute Maximum Ratings on Page 27, combinations of CLKIN and clock multipliers must not select core/peripheral clocks that exceed maximum operating conditions. ...
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... ARDY DATA 15–0 Figure 12. Asynchronous Memory Read Cycle Timing with Synchronous ARDY and Figure PROGRAMMED READ ACCESS EXTENDED ACCESS 4 CYCLES 3 CYCLES SARDY HARDY t SARDY Rev Page July 2010 ADSP-BF538/ADSP-BF538F Min Max 2.1 0.8 4.0 0.0 6.0 0.8 HOLD 1 CYCLE HARDY t SDAT t ...
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... ADSP-BF538/ADSP-BF538F Table 24. Asynchronous Memory Read Cycle Timing with Asynchronous ARDY Parameter Timing Requirements t DATA15–0 Setup Before CLKOUT SDAT t DATA15–0 Hold After CLKOUT HDAT t ARDY Negated Delay from AMSx Asserted DANR t ARDY Asserted Hold After ARE Negated HAA Switching Characteristic ...
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... DATA 15–0 Figure 14. Asynchronous Memory Write Cycle Timing with Synchronous ARDY and Figure PROGRAMMED ACCESS SETUP WRITE ACCESS EXTEND HOLD 2 CYCLES 2 CYCLES 1 CYCLE 1 CYCLE SARDY HARDY t HARDY t SARDY Rev Page July 2010 ADSP-BF538/ADSP-BF538F Min Max 4.0 0.0 6.0 1.0 6.0 0 DDAT Unit ...
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... ADSP-BF538/ADSP-BF538F Table 26. Asynchronous Memory Write Cycle Timing with Asynchronous ARDY Parameter Timing Requirements t ARDY Negated Delay from AMSx Asserted DANR t ARDY Asserted Hold After ARE Negated HAA Switching Characteristics t DATA15–0 Disable After CLKOUT DDAT t DATA15–0 Enable After CLKOUT ENDAT ...
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... ADDRESS (OUT SCLK t t SSDAT HSDAT t t ENSDAT t DCAD NOTE: COMMAND = SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE. Figure 16. SDRAM Interface Timing Rev Page July 2010 ADSP-BF538/ADSP-BF538F Min Max 2.1 0.8 7.5 2.5 2.5 6.0 0.8 6.0 1 SCLKL SCLKH t DCAD DSDAT ...
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... ADSP-BF538/ADSP-BF538F External Port Bus Request and Grant Cycle Timing Table 28 and Table 29 on Page 35 and Figure 17 on Page 35 describe external port bus request and grant cycle operations for synchronous and for asynchronous BR. Table 28. External Port Bus Request and Grant Cycle Timing with Synchronous BR ...
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... CLKOUT High to BGH High Setup DBH t CLKOUT High to BGH Deasserted Hold Time EBH CLKOUT BR AMSx ADDR 19-1 ABE1-0 AWE ARE BG BGH Figure 18. External Port Bus Request and Grant Cycle Timing with Asynchronous BR ADSP-BF538/ADSP-BF538F t WBR DBG t DBH Rev Page July 2010 Min ...
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... ADSP-BF538/ADSP-BF538F Parallel Peripheral Interface Timing Table 30 and Figure 19, Figure 20, Figure describe parallel peripheral interface operations. Table 30. Parallel Peripheral Interface Timing Parameter Timing Requirements t PPI_CLK Width PCLKW 1 t PPI_CLK Period PCLK t External Frame Sync Setup Before PPI_CLK SFSPE t External Frame Sync Hold After PPI_CLK ...
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... PPI_DATA Figure 21. PPI GP Tx Mode with External Frame Sync Timing FRAME SYNC DRIVEN PPI_CLK t DFSPE t HOFSPE PPI_FS1/2 PPI_DATA Figure 22. PPI GP Tx Mode with Internal Frame Sync Timing Rev Page July 2010 ADSP-BF538/ADSP-BF538F t t HFSPE PCLKW t PCLK DATA DATA DRIVEN DRIVEN t PCLK ...
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... ADSP-BF538/ADSP-BF538F Serial Port Timing Table 30 through Table 34 on Page 41 and through Figure 26 on Page 41 describe serial port operations. Table 31. Serial Ports—External Clock Parameter Timing Requirements t TFSx/RFSx Setup Before TSCLKx/RSCLKx (Externally Generated TFSx/RFSx) SFSE t TFSx/RFSx Hold After TSCLKx/RSCLKx (Externally Generated TFSx/RFSx) ...
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... TSCLKx t HOFSE TFSx (OUTPUT) t HFSI TFSx (INPUT) t HDTE DTx Figure 23. Serial Ports t SUDTE t SUDRE FIRST TSCLKx/RSCLKx EDGE AFTER SPORT ENABLED Rev Page July 2010 ADSP-BF538/ADSP-BF538F SAMPLE EDGE t SCLKE t SCLKEW t DFSE t t SFSE HFSE t t HDRE SDRE SAMPLE EDGE t SCLKE t SCLKEW t DFSE ...
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... ADSP-BF538/ADSP-BF538F Table 33. Serial Ports—Enable and Three-State Parameter Switching Characteristics t Data Enable Delay from External TSCLKx DTENE t Data Disable Delay from External TSCLKx DDTTE t Data Enable Delay from Internal TSCLKx DTENI t Data Disable Delay from Internal TSCLKx DDTTI 1 Referenced to drive edge. ...
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... DDTTE/I DTENE/I DRIVE SAMPLE DRIVE EDGE EDGE EDGE t DDTLFSE t DTENLFSE 1ST BIT DRIVE SAMPLE DRIVE EDGE EDGE EDGE t DDTLFSE 1ST BIT Figure 26. External Late Frame Sync Rev Page July 2010 ADSP-BF538/ADSP-BF538F Min Max 1, 2 10.0 0 and t apply. DDTLFSE DTENLFS Unit ns ns ...
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... ADSP-BF538/ADSP-BF538F Serial Peripheral Interface Ports—Master Timing Table 35 and Figure 27 describe SPI ports master operations. Table 35. Serial Peripheral Interface (SPI) Ports—Master Timing Parameter Timing Requirements t Data Input Valid to SCKx Edge (Data Input Setup) SSPIDM t SCKx Sampling Edge to Data Input Invalid ...
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... SPICLS SPICHS t DDSPID t HDSPID t HSPID t t HDSPID DDSPID t SSPID Figure 28. Serial Peripheral Interface (SPI) Ports—Slave Timing Rev Page July 2010 ADSP-BF538/ADSP-BF538F Min Max 2 × t –1.5 SCLK 2 × t –1.5 SCLK 4 × t SCLK 2 × t –1.5 SCLK 2 × t –1.5 SCLK 2 × t –1.5 SCLK 2 ...
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... ADSP-BF538/ADSP-BF538F General-Purpose Port Timing Table 37 and Figure 29 describe general-purpose operations. Table 37. General-Purpose Port Timing Parameter Timing Requirement t GP Port Pin Input Pulse Width WFI Switching Characteristic t GP Port Pin Output Delay from CLKOUT Low GPOD CLKOUT GPIO OUTPUT GPIO INPUT Timer Cycle Timing ...
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... Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing For information on the UART port receive and transmit opera- tions, see the ADSP-BF538 Blackfin Processor Hardware Reference. JTAG Test and Emulation Port Timing Table 39 and Figure 31 describe JTAG port operations. Table 39. JTAG Port Timing ...
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... ADSP-BF538/ADSP-BF538F OUTPUT DRIVE CURRENTS Figure 32 through Figure 39 on Page 47 voltage characteristics for the output drivers of the ADSP- BF538/ADSP-BF538F processors. The curves represent the cur- rent drive capability of the output drivers as a function of output voltage. 120 100 100 0 0.5 1.0 1.5 SOURCE VOLTAGE (V) Figure 32 ...
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... V = 3.3 V 100 DDEXT V = 3.6 V DDEXT 100 150 0 3.0 3.5 4.0 ) Rev Page July 2010 ADSP-BF538/ADSP-BF538F V = 2.75V DDEXT 0.5 1.0 1.5 2.0 SOURCE VOLTAGE (V) Figure 38. Drive Current D (Low V ) DDEXT V DDEXT V DDEXT V DDEXT 0.5 1.0 1.5 2.0 2.5 3.0 SOURCE VOLTAGE (V) Figure 39. Drive Current D (High V ...
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... ADSP-BF538/ADSP-BF538F 0.5 1.0 1.5 SOURCE VOLTAGE (V) Figure 40. Drive Current E (Low 0.5 1.0 1.5 2.0 SOURCE VOLTAGE (V) Figure 41. Drive Current E (High V TEST CONDITIONS All timing parameters appearing in this data sheet were mea- sured under the conditions described in this section. shows the measurement point for ac measurements (except out- put enable/disable) ...
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... To determine the data output hold time in a particular system, using the equation given above. Choose ΔV first calculate t DECAY to be the difference between the ADSP-BF538/ADSP-BF538F processor’s output voltage and the input threshold for the device requiring the hold time the total bus capacitance ...
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... ADSP-BF538/ADSP-BF538F 12 10 RISE TIME 100 150 LOAD CAPACITANCE (pF) Figure 47. Typical Rise and Fall Times (10% to 90%) vs. Load Capacitance for Driver 2.7 V (Min) DDEXT RISE TIME 100 150 LOAD CAPACITANCE (pF) Figure 48. Typical Rise and Fall Times (10% to 90%) vs. Load Capacitance for Driver ...
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... Figure 53. Typical Fall Time (10% to 90%) vs. Load Capacitance for Driver E 124 120 116 FALL TIME 112 108 104 200 250 100 0 Figure 54. Typical Fall Time (10% to 90%) vs. Load Capacitance for Driver E Rev Page July 2010 ADSP-BF538/ADSP-BF538F FALL TIME 50 100 150 200 LOAD CAPACITANCE (pF 2.7 V (Min) DDEXT FALL TIME 50 100 150 ...
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... ADSP-BF538/ADSP-BF538F THERMAL CHARACTERISTICS To determine the junction temperature on the application printed circuit board use ( Ψ CASE JT where junction temperature (8C case temperature (8C) measured by customer at top cen- CASE ter of package. Ψ = from Table 40 or Table power dissipation (see Electrical Characteristics on Page 25 D for the method to calculate P ...
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... Figure 55. 316-Ball CSP_BGA Ball Assignment (Top View VDDINT NC VDDEXT FLASH CONTROL Figure 56. 316-Ball CSP_BGA Ball Assignment (Bottom View) Rev Page July 2010 ADSP-BF538/ADSP-BF538F A1 BALL GND VDDRTC NC FLASH CONTROL VROUTx I/O Note: H18 and Y14 are NC for ADSP-BF538 and I/O (FCE and RESET) for ADSP-538F. ...
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... ADSP-BF538/ADSP-BF538F Table 42. 316-Ball CSP_BGA Ball Assignment (Numerically by Ball Number) Ball No. Signal Ball No. Signal A1 GND C7 SPI2SEL1 F8 A2 PF10 C8 SPI2SS A3 PF11 C9 MOSI2 A4 PPI_CLK C10 MISO2 A5 PPI0 C11 SCK2 A6 PPI2 C12 V DDINT A7 PF15 C13 SPI1SEL1 F14 A8 PF13 C14 MISO1 A9 V C15 SPI1SS DDRTC A10 ...
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... R11 PPI0 GND J12 GND R12 PPI1 GND J13 GND R13 PPI2 GND J14 GND T3 PPI3 GND K7 GND U3 RESET Rev Page July 2010 ADSP-BF538/ADSP-BF538F Ball No. Signal V2 RFS0 P2 TX0 V3 RFS1 K1 TX1 V6 RFS2 Y11 TX2 V17 RFS3 T18 V DDEXT V18 RSCLK0 R2 V DDEXT ...
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... ADSP-BF538BBCZ-4A –40°C to +85°C 400 MHz ADSP-BF538BBCZ-5A –40°C to +85°C 533 MHz ADSP-BF538BBCZ-4F8 –40°C to +85°C 400 MHz ADSP-BF538BBCZ-5F8 –40°C to +85°C 533 MHz RoHS compliant part. 2 Referenced temperature is ambient temperature. ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners ...