ADSP-BF538BBCZ-5F4 Analog Devices Inc, ADSP-BF538BBCZ-5F4 Datasheet - Page 12

• Manufacturer Part Number: ADSP-BF538BBCZ-5F4
• Description: IC, FLOAT-PT DSP, 16BIT, 533MHZ, BGA-316
• Manufacturer: Analog Devices Inc
• Series: Blackfinr
• Type: Fixed Pointr

Specifications of ADSP-BF538BBCZ-5F4

• No. Of Bits: 16 Bit
• Frequency: 533MHz
• Supply Voltage: 1.25V
• Embedded Interface Type: CAN, I2C, PPI, SPI, TWI, UART
• No. Of I/o's: 54
• Flash Memory Size: 512KB
• Interface: CAN, SPI, SSP, TWI, UART
• Clock Rate: 533MHz
• Non-volatile Memory: FLASH (512 kB)
• On-chip Ram: 148kB
• Voltage - I/o: 3.00V, 3.30V
• Voltage - Core: 1.25V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 316-CSPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: ADZS-BFAUDIO-EZEXT - BOARD EVAL AUDIO BLACKFIN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

ADSP-BF538/ADSP-BF538F
The PPI supports a variety of general-purpose and ITU-R 656
modes of operation. In general-purpose mode, the PPI provides
half-duplex, bidirectional data transfer with up to 16 bits of
data. Up to 3 frame synchronization signals are also provided.
In ITU-R 656 mode, the PPI provides half-duplex, bi-direc-
tional transfer of 8- or 10-bit video data. Additionally, on-chip
decode of embedded start-of-line (SOL) and start-of-field (SOF)
preamble packets is supported.
General-Purpose Mode Descriptions
The general-purpose modes of the PPI are intended to suit a
wide variety of data capture and transmission applications.
Three distinct submodes are supported:
Input Mode
Input mode is intended for ADC applications, as well as video
communication with hardware signaling. In its simplest form,
PPI_FS1 is an external frame sync input that controls when to
read data. The PPI_DELAY MMR allows for a delay (in
PPI_CLK cycles) between reception of this frame sync and the
initiation of data reads. The number of input data samples is
user programmable and defined by the contents of the
PPI_COUNT register. The PPI supports 8-bit, and 10-bit
through 16-bit data, and is programmable in the
PPI_CONTROL register.
Frame Capture Mode
Frame capture mode allows the video source(s) to act as a slave
(e.g., for frame capture). The ADSP-BF538/ADSP-BF538F pro-
cessors control when to read from the video source(s). PPI_FS1
is an HSYNC output and PPI_FS2 is a VSYNC output.
Output Mode
Output mode is used for transmitting video or other data with
up to three output frame syncs. Typically, a single frame sync is
appropriate for data converter applications, whereas two or
three frame syncs could be used for sending video with hard-
ware signaling.
ITU-R 656 Mode Descriptions
The ITU-R 656 modes of the PPI are intended to suit a wide
variety of video capture, processing, and transmission applica-
tions. Three distinct submodes are supported:
Active Video Only Mode
Active video only mode is used when only the active video por-
tion of a field is of interest and not any of the blanking intervals.
The PPI does not read in any data between the end of active
• Input mode – frame syncs and data are inputs into the PPI.
• Frame capture mode – frame syncs are outputs from the
• Output mode – frame syncs and data are outputs from the
• Active video only mode
• Vertical blanking only mode
• Entire field mode
PPI, but data are inputs.
PPI.
Rev. D | Page 12 of 56 | July 2010
video (EAV) and start of active video (SAV) preamble symbols,
or any data present during the vertical blanking intervals. In this
mode, the control byte sequences are not stored to memory;
they are filtered by the PPI. After synchronizing to the start of
Field 1, the PPI ignores incoming samples until it sees an SAV
code. The user specifies the number of active video lines per
frame (in PPI_COUNT register).
Vertical Blanking Interval Mode
In this mode, the PPI only transfers vertical blanking interval
(VBI) data.
Entire Field Mode
In this mode, the entire incoming bit stream is read in through
the PPI. This includes active video, control preamble sequences,
and ancillary data that may be embedded in horizontal and ver-
tical blanking intervals. Data transfer starts immediately after
synchronization to Field 1.
CONTROLLER AREA NETWORK (CAN) INTERFACE
The ADSP-BF538/ADSP-BF538F processors provide a CAN
controller that is a communication controller implementing the
Controller Area Network (CAN) V2.0B protocol. This protocol
is an asynchronous communications protocol used in both
industrial and automotive control systems. CAN is well suited
for control applications due to its capability to communicate
reliably over a network since the protocol incorporates CRC
checking, message error tracking, and fault node confinement.
The CAN controller is based on a 32-entry mailbox RAM and
supports both the standard and extended identifier (ID) mes-
sage formats specified in the CAN protocol specification,
revision 2.0, part B.
Each mailbox consists of eight 16-bit data words. The data is
divided into fields, which includes a message identifier, a time
stamp, a byte count, up to 8 bytes of data, and several control
bits. Each node monitors the messages being passed on the net-
work. If the identifier in the transmitted message matches an
identifier in one of its mailboxes, then the module knows that
the message was meant for it, passes the data into its appropriate
mailbox, and signals the processor of message arrival with an
interrupt.
The CAN controller can wake up the processor from sleep mode
upon generation of a wake-up event, such that the processor can
be maintained in a low power mode during idle conditions.
Additionally, a CAN wake-up event can wake up the on-chip
internal voltage regulator from the powered-down
hibernate state.
The electrical characteristics of each network connection are
very stringent, therefore the CAN interface is typically divided
into 2 parts: a controller and a transceiver. This allows a single
controller to support different drivers and CAN networks. The
ADSP-BF538/ADSP-BF538F CAN module represents the con-
troller part of the interface. This module’s network I/O is a
single transmit output and a single receive input, which connect
to a line transceiver.