PC28F128P33T85A NUMONYX, PC28F128P33T85A Datasheet - Page 68

• Manufacturer Part Number: PC28F128P33T85A
• Description: IC FLASH 128MBIT 85NS 64EZBGA
• Manufacturer: NUMONYX
• Series: StrataFlash™r

Specifications of PC28F128P33T85A

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 128M (8Mx16)
• Speed: 85ns
• Interface: Parallel
• Voltage - Supply: 2.3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TBGA
• Cell Type: NOR
• Density: 128Mb
• Access Time (max): 85ns
• Interface Type: Parallel/Serial
• Boot Type: Top
• Address Bus: 23b
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: EZBGA
• Sync/async: Async/Sync
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.3V
• Operating Supply Voltage (max): 3.6V
• Word Size: 16b
• Number Of Words: 8M
• Supply Current: 28mA
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 888065; 888065; PC28F128P33T85 888065

11.4.8.2
Note:
11.4.8.3
Caution:
Datasheet
68
page
register to be read.
address offsets of the Protection Registers and Lock Registers. PR data is read 16 bits
at a time.
Programming the Protection Registers
To program any of the Protection Registers, first issue the Program Protection Register
command at the parameter’s base address plus the offset to the desired Protection
Register (see
desired Protection Register data to the same Protection Register address (see
Figure 32, “Protection Register Map” on page
The device programs the 64-bit and 128-bit user-programmable Protection Register
data 16 bits at a time (see
page
Register’s address space causes a program error (SR[4] set). Attempting to program a
locked Protection Register causes a program error (SR[4] set) and a lock error (SR[1]
set).
When programming the OTP bits in the protection registers for a Top Parameter
Device, the following upper address bits must also be driven properly: A[Max:17]
driven high (V
for QUAD+ SCSP.
Locking the Protection Registers
Each Protection Register can be locked by programming its respective lock bit in the
Lock Register. To lock a Protection Register, program the corresponding bit in the Lock
Register by issuing the Program Lock Register command, followed by the desired Lock
Register data (see
physical addresses of the Lock Registers are 0x80 for register 0 and 0x89 for register 1.
These addresses are used when programming the lock registers (see
Identifier Information” on page
Bit 0 of Lock Register 0 is already programmed during the manufacturing process at the
“factory”, locking the lower, pre-programmed 64-bit region of the first 128-bit
Protection Register containing the unique identification number of the device. Bit 1 of
Lock Register 0 can be programmed by the user to lock the user-programmable, 64-bit
region of the first 128-bit Protection Register. When programming Bit 1 of Lock Register
0, all other bits need to be left as ‘1’ such that the data programmed is 0xFFFD.
Lock Register 1 controls the locking of the upper sixteen 128-bit Protection Registers.
Each of the 16 bits of Lock Register 1 correspond to each of the upper sixteen 128-bit
Protection Registers. Programming a bit in Lock Register 1 locks the corresponding
128-bit Protection Register.
After being locked, the Protection Registers cannot be unlocked.
44). Next, perform a read operation using the address offset corresponding to the
76). Issuing the Program Protection Register command outside of the Protection
Section 9.6, “Device Command Bus Cycles” on page
IH
) for TSOP and Easy BGA packages, and A[Max:16] driven high (V
Section 9.6, “Device Command Bus Cycles” on page
Table 30, “Device Identifier Information” on page 56
Figure 40, “Protection Register Programming Flowchart” on
56).
Numonyx™ StrataFlash
67).
®
Embedded Memory (P33)
Order Number: 314749-05
44). Next, write the
Table 30, “Device
44). The
shows the
November 2007
IH
)