PC28F128P33T85A NUMONYX, PC28F128P33T85A Datasheet - Page 46

• Manufacturer Part Number: PC28F128P33T85A
• Description: IC FLASH 128MBIT 85NS 64EZBGA
• Manufacturer: NUMONYX
• Series: StrataFlash™r

Specifications of PC28F128P33T85A

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 128M (8Mx16)
• Speed: 85ns
• Interface: Parallel
• Voltage - Supply: 2.3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TBGA
• Cell Type: NOR
• Density: 128Mb
• Access Time (max): 85ns
• Interface Type: Parallel/Serial
• Boot Type: Top
• Address Bus: 23b
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: EZBGA
• Sync/async: Async/Sync
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.3V
• Operating Supply Voltage (max): 3.6V
• Word Size: 16b
• Number Of Words: 8M
• Supply Current: 28mA
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 888065; 888065; PC28F128P33T85 888065

10.0
Table 24: Command Codes and Definitions (Sheet 1 of 2)
Datasheet
46
Suspend
Mode
Erase
Write
Write
Read
Command Definitions
Table 24
Code
0xD0
0xD0
0xD0
0xB0
0xD0
0xFF
0x70
0x90
0x98
0x50
0x40
0x10
0xE8
0x80
0x20
Read Array
Read Status
Register
Read Device ID
or Configuration
Register
Read Query
Clear Status
Register
Word Program
Setup
Alternate Word
Program Setup
Buffered Program
Buffered Program
Confirm
BEFP Setup
BEFP Confirm
Block Erase Setup
Block Erase Confirm
Program or Erase
Suspend
Suspend Resume
shows valid device command codes and descriptions.
Device Mode
Places the device in Read Array mode. Array data is output on DQ[15:0].
Places the device in Read Status Register mode. The device enters this mode
after a program or erase command is issued. SR data is output on DQ[7:0].
Places device in Read Device Identifier mode. Subsequent reads output
manufacturer/device codes, Configuration Register data, Block Lock status,
or Protection Register data on DQ[15:0].
Places the device in Read Query mode. Subsequent reads output Common
Flash Interface information on DQ[7:0].
The WSM can only set SR error bits. The Clear Status Register command is
used to clear the SR error bits.
First cycle of a 2-cycle programming command; prepares the CUI for a write
operation. On the next write cycle, the address and data are latched and the
WSM executes the programming algorithm at the addressed location. During
program operations, the device responds only to Read Status Register and
Program Suspend commands. CE# or OE# must be toggled to update the
Status Register in asynchronous read. CE# or ADV# must be toggled to
update the SR Data for synchronous Non-array reads. The Read Array
command must be issued to read array data after programming has finished.
Equivalent to the Word Program Setup command, 0x40.
This command loads a variable number of words up to the buffer size of 32
words onto the program buffer.
The confirm command is Issued after the data streaming for writing into the
buffer is done. This instructs the WSM to perform the Buffered Program
algorithm, writing the data from the buffer to the flash memory array.
First cycle of a 2-cycle command; initiates the BEFP mode. The CUI then
waits for the BEFP Confirm command, 0xD0, that initiates the BEFP
algorithm. All other commands are ignored when BEFP mode begins.
If the previous command was BEFP Setup (0x80), the CUI latches the
address and data, and prepares the device for BEFP mode.
First cycle of a 2-cycle command; prepares the CUI for a block-erase
operation. The WSM performs the erase algorithm on the block addressed by
the Erase Confirm command. If the next command is not the Erase Confirm
(0xD0) command, the CUI sets Status Register bits SR [5,4], and places the
device in Read Status Register mode.
If the first command was Block Erase Setup (0x20), the CUI latches the
address and data, and the WSM erases the addressed block. During block-
erase operations, the device responds only to Read Status Register and Erase
Suspend commands. CE# or OE# must be toggled to update the Status
Register in asynchronous read. CE# or ADV# must be toggled to update the
SR Data for synchronous Non-array reads.
This command issued to any device address initiates a suspend of the
currently-executing program or block erase operation. The Status Register
indicates successful suspend operation by setting either SR 2 (program
suspended) or SR 6 (erase suspended), along with SR 7 (ready). The WSM
remains in the suspend mode regardless of control signal states (except for
RST# asserted).
This command issued to any device address resumes the suspended program
or block-erase operation.
Numonyx™ StrataFlash
Description
®
Embedded Memory (P33)
Order Number: 314749-05
November 2007