PC28F128P33T85A NUMONYX, PC28F128P33T85A Datasheet - Page 50

• Manufacturer Part Number: PC28F128P33T85A
• Description: IC FLASH 128MBIT 85NS 64EZBGA
• Manufacturer: NUMONYX
• Series: StrataFlash™r

Specifications of PC28F128P33T85A

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 128M (8Mx16)
• Speed: 85ns
• Interface: Parallel
• Voltage - Supply: 2.3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TBGA
• Cell Type: NOR
• Density: 128Mb
• Access Time (max): 85ns
• Interface Type: Parallel/Serial
• Boot Type: Top
• Address Bus: 23b
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: EZBGA
• Sync/async: Async/Sync
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.3V
• Operating Supply Voltage (max): 3.6V
• Word Size: 16b
• Number Of Words: 8M
• Supply Current: 28mA
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 888065; 888065; PC28F128P33T85 888065

Table 26: Read Configuration Register Description (Sheet 2 of 2)
11.1.0.2
11.1.0.3
Datasheet
50
10
9
8
7
6
5:4
3
2:0
Note:
Latency Code 2, Data Hold for a 2-clock data cycle (DH = 1) WAIT must be deasserted with valid data (WD = 0).
Latency Code 2, Data Hold for a 2-cock data cycle (DH=1) WAIT deasserted one data cycle before valid data (WD = 1)
combination is not supported.
Table 26, “Read Configuration Register Description”
and TSOP packages, the table reference should be adjusted using address bits A[16:1].
Wait Polarity (WP)
Data Hold (DH)
Wait Delay (WD)
Burst Sequence (BS)
Clock Edge (CE)
Reserved (R)
Burst Wrap (BW)
Burst Length (BL[2:0])
Read Mode
The Read Mode (RM) bit selects synchronous burst-mode or asynchronous page-mode
operation for the device. When the RM bit is set, asynchronous page mode is selected
(default). When RM is cleared, synchronous burst mode is selected.
Latency Count
The Latency Count (LC) bits tell the device how many clock cycles must elapse from the
rising edge of ADV# (or from the first valid clock edge after ADV# is asserted) until the
first valid data word is driven onto DQ[15:0]. The input clock frequency is used to
determine this value and
settings of LC. The maximum Latency Count for P33 would be Code 4 based on the Max
clock frequency specification of 52 Mhz, and there will be zero WAIT States when
bursting within the word line. Please also refer to
(EOWL) Considerations” on page 55
Refer to
Table 27, “LC and Frequency Support” on page 51
0 =WAIT signal is active low
1 =WAIT signal is active high (default)
0 =Data held for a 1-clock data cycle
1 =Data held for a 2-clock data cycle (default)
0 =WAIT deasserted with valid data
1 =WAIT deasserted one data cycle before valid data (default)
0 =Reserved
1 =Linear (default)
0 = Falling edge
1 = Rising edge (default)
Reserved bits should be cleared (0)
0 =Wrap; Burst accesses wrap within burst length set by BL[2:0]
1 =No Wrap; Burst accesses do not wrap within burst length (default)
001 =4-word burst
010 =8-word burst
011 =16-word burst
111 =Continuous-word burst (default)
(Other bit settings are reserved)
Figure 27
shows the data output latency for the different
for more information on EOWL.
Numonyx™ StrataFlash
is shown using the QUAD+ package. For EASY BGA
Section 11.1.0.12, “End of Word Line
for Latency Code Settings.
®
Embedded Memory (P33)
Order Number: 314749-05
November 2007