PC28F128P33T85A NUMONYX, PC28F128P33T85A Datasheet - Page 60

• Manufacturer Part Number: PC28F128P33T85A
• Description: IC FLASH 128MBIT 85NS 64EZBGA
• Manufacturer: NUMONYX
• Series: StrataFlash™r

Specifications of PC28F128P33T85A

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 128M (8Mx16)
• Speed: 85ns
• Interface: Parallel
• Voltage - Supply: 2.3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TBGA
• Cell Type: NOR
• Density: 128Mb
• Access Time (max): 85ns
• Interface Type: Parallel/Serial
• Boot Type: Top
• Address Bus: 23b
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: EZBGA
• Sync/async: Async/Sync
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.3V
• Operating Supply Voltage (max): 3.6V
• Word Size: 16b
• Number Of Words: 8M
• Supply Current: 28mA
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 888065; 888065; PC28F128P33T85 888065

11.3.3.1
Note:
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3.
4.
11.3.3.2
Note:
11.3.3.3
Datasheet
60
Word buffer boundaries in the array are determined by A[4:0] (0x00 through 0x1F). The alignment start point is A[4:0] =
0x00.
Some degradation in performance may occur if this limit is exceeded, but the internal algorithm continues to work
properly.
If the internal address counter increments beyond the block's maximum address, addressing wraps around to the
beginning of the block.
If the number of words is less than 32, remaining locations must be filled with 0xFFFF.
With adequate continuity testing, programming equipment can rely on the WSM’s
internal verification to ensure that the device has programmed properly. This eliminates
the external post-program verification and its associated overhead.
BEFP Requirements and Considerations
BEFP requirements:
BEFP considerations:
BEFP Setup Phase
After receiving the BEFP Setup and Confirm command sequence, Status Register bit
SR[7] (Ready) is cleared, indicating that the WSM is busy with BEFP algorithm startup.
A delay before checking SR[7] is required to allow the WSM enough time to perform all
of its setups and checks (Block-Lock status, V
SR[4] is set and BEFP operation terminates. If the block was found to be locked, SR[1]
is also set. SR[3] is set if the error occurred due to an incorrect V
Reading from the device after the BEFP Setup and Confirm command sequence outputs
Status Register data. Do not issue the Read Status Register command; it will be
interpreted as data to be loaded into the buffer.
BEFP Program/Verify Phase
After the BEFP Setup Phase has completed, the host programming system must check
SR[7,0] to determine the availability of the write buffer for data streaming. SR[7]
cleared indicates the device is busy and the BEFP program/verify phase is activated.
SR[0] indicates the write buffer is available.
Two basic sequences repeat in this phase: loading of the write buffer, followed by buffer
data programming to the array. For BEFP, the count value for buffer loading is always
the maximum buffer size of 32 words. During the buffer-loading sequence, data is
• Case temperature: T
• V
• VPP driven to V
• Target block unlocked before issuing the BEFP Setup and Confirm commands
• The first-word address for the block to be programmed must be held constant from
• The first-word address must align with the start of an array buffer boundary
• For optimum performance, cycling must be limited below 100 erase cycles per
• BEFP programs one block at a time; all buffer data must fall within a single block
• BEFP cannot be suspended
• Programming to the flash memory array can occur only when the buffer is full
the setup phase through all data streaming into the target block, until transition to
the exit phase is desired
block
CC
within specified operating range
2
PPH
C
= 25 °C ± 5 °C
Numonyx™ StrataFlash
PP
level, etc.). If an error is detected,
®
Embedded Memory (P33)
PP
Order Number: 314749-05
level.
November 2007
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