PC28F128P33T85A NUMONYX, PC28F128P33T85A Datasheet - Page 47

• Manufacturer Part Number: PC28F128P33T85A
• Description: IC FLASH 128MBIT 85NS 64EZBGA
• Manufacturer: NUMONYX
• Series: StrataFlash™r

Specifications of PC28F128P33T85A

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 128M (8Mx16)
• Speed: 85ns
• Interface: Parallel
• Voltage - Supply: 2.3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TBGA
• Cell Type: NOR
• Density: 128Mb
• Access Time (max): 85ns
• Interface Type: Parallel/Serial
• Boot Type: Top
• Address Bus: 23b
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: EZBGA
• Sync/async: Async/Sync
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.3V
• Operating Supply Voltage (max): 3.6V
• Word Size: 16b
• Number Of Words: 8M
• Supply Current: 28mA
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 888065; 888065; PC28F128P33T85 888065

Numonyx™ StrataFlash
Table 24: Command Codes and Definitions (Sheet 2 of 2)
November 2007
Order Number: 314749-05
Block Locking/
Configuration
Protection
Unlocking
Mode
Code
0xD0
0xC0
0x60
0x01
0x60
0x03
0x2F
®
Embedded Memory (P33)
Lock Block Setup
Lock Block
Unlock Block
Lock-Down Block
Program Protection
Register Setup
Read Configuration
Register Setup
Read Configuration
Register
Device Mode
First cycle of a 2-cycle command; prepares the CUI for block lock
configuration changes. If the next command is not Block Lock (0x01), Block
Unlock (0xD0), or Block Lock-Down (0x2F), the CUI sets SR [5,4], indicating
a command sequence error.
If the previous command was Block Lock Setup (0x60), the addressed block
is locked.
If the previous command was Block Lock Setup (0x60), the addressed block
is unlocked. If the addressed block is in a lock-down state, the operation has
no effect.
If the previous command was Block Lock Setup (0x60), the addressed block
is locked down.
First cycle of a 2-cycle command; prepares the device for a Protection
Register or Lock Register program operation. The second cycle latches the
register address and data, and starts the programming algorithm.
First cycle of a 2-cycle command; prepares the CUI for device read
configuration. If the Set Read Configuration Register command (0x03) is not
the next command, the CUI sets Status Register bits SR[5,4], indicating a
command sequence error.
If the previous command was Read Configuration Register Setup (0x60), the
CUI latches the address and writes A[15:0] (QUAD+) or A[16:1] (EASY BGA/
TSOP) to the Read Configuration Register. Following a Configure RCR
command, subsequent read operations access array data.
Description
Datasheet
47