PC28F128P33T85A NUMONYX, PC28F128P33T85A Datasheet - Page 41

• Manufacturer Part Number: PC28F128P33T85A
• Description: IC FLASH 128MBIT 85NS 64EZBGA
• Manufacturer: NUMONYX
• Series: StrataFlash™r

Specifications of PC28F128P33T85A

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 128M (8Mx16)
• Speed: 85ns
• Interface: Parallel
• Voltage - Supply: 2.3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TBGA
• Cell Type: NOR
• Density: 128Mb
• Access Time (max): 85ns
• Interface Type: Parallel/Serial
• Boot Type: Top
• Address Bus: 23b
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: EZBGA
• Sync/async: Async/Sync
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.3V
• Operating Supply Voltage (max): 3.6V
• Word Size: 16b
• Number Of Words: 8M
• Supply Current: 28mA
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 888065; 888065; PC28F128P33T85 888065

Numonyx™ StrataFlash
8.0
8.1
8.2
Table 21: Power and Reset
November 2007
Order Number: 314749-05
Notes:
1.
2.
3.
4.
5.
6.
7.
Num
P1
P2
P3
t
t
t
These specifications are valid for all device versions (packages and speeds).
The device may reset if t
Not applicable if RST# is tied to Vcc.
Sampled, but not 100% tested.
When RST# is tied to the V
When RST# is tied to the V
Reset completes within t
Symbol
PLPH
PLRH
VCCPH
Power and Reset Specifications
Power-Up and Power-Down
Power supply sequencing is not required if VPP is connected to VCC or VCCQ. Otherwise
V
Power supply transitions should only occur when RST# is low. This protects the device
from accidental programming or erasure during power transitions.
Reset Specifications
Asserting RST# during a system reset is important with automated program/erase
devices because systems typically expect to read from flash memory when coming out
of reset. If a CPU reset occurs without a flash memory reset, proper CPU initialization
may not occur. This is because the flash memory may be providing status information,
instead of array data as expected. Connect RST# to the same active low reset signal
used for CPU initialization.
Also, because the device is disabled when RST# is asserted, it ignores its control inputs
during power-up/down. Invalid bus conditions are masked, providing a level of memory
protection.
CC
RST# pulse width low
RST# low to device reset during erase
RST# low to device reset during program
and V
V
V
®
CC
CC
Embedded Memory (P33)
Power valid to RST# de-assertion (high)
Power valid to RST# de-assertion (high)
CCQ
PLPH
PLPH
should attain their minimum operating voltage before applying V
CC
CCQ
if RST# is asserted while no erase or program operation is executing.
is < t
supply, device will not be ready until t
supply, device will not be ready until t
Parameter
130nm
65nm
PLPH MIN
, but this is not guaranteed.
VCCPH
VCCPH
Min
100
300
90
-
-
after V
after V
CC
CC
Max
≥ V
25
25
≥ V
-
-
-
CCMIN
CCMIN
.
..
Unit
ns
µs
PP
1,2,3,4
1,3,4,7
1,3,4,7
1,4,5,6
Notes
Datasheet
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41