ML610Q429-NNNTBZ03A7 Rohm Semiconductor, ML610Q429-NNNTBZ03A7 Datasheet - Page 42

• Manufacturer Part Number: ML610Q429-NNNTBZ03A7
• Description: MCU 8BIT 48K FLASH 128-TQFP
• Manufacturer: Rohm Semiconductor

Specifications of ML610Q429-NNNTBZ03A7

• Core Processor: nX-U8/100
• Core Size: 8-Bit
• Speed: 4.2MHz
• Connectivity: I²C, SSP, UART/USART
• Peripherals: LCD, Melody Driver, POR, PWM, WDT
• Number Of I /o: 20
• Program Memory Size: 48KB (24K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 2x12b, 2x24b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

3.3
3.3.1
(1) The power circuit is initialized, but not initialized by the reset by the BRK instruction execution. For the details of
(2) All the special function registers (SFRs) whose initial value is not undefined are initialized. However, the
(3) CPU is initialized.
Note:
In system reset mode, the contents of data memory and those of any SFR whose initial value is undefined are not
initialized and are undefined. Initialize them by software.
In system reset mode by the BRK instruction, no special function register (SFR) that has a fixed initial value is
initialized either. Therefore initialize such an SFR by software.
System reset has the highest priority among all the processings and any other processing being executed up to then is
cancelled.
The system reset mode is set by any of the following causes.
In system reset mode, the following processing is performed.
• Reset by the RESET_N pin
• Reset by power-on detection
• Reset by low-speed oscillation stop detection
• Reset by watchdog timer (WDT) overflow
• Software reset by the BRK instruction (only the CPU is reset)
the power circuit, refer to Chapter 26, “Power Circuit”.
initialization is not performed by software reset due to execution of the BRK instruction. See Appendix A
“Registers” for the initial values of the SFRs.
• All the registers in CPU are initialized.
• The contents of addresses 0000H and 0001H in the program memory are set to the stack pointer (SP).
• The contents of addresses 0002H and 0003H in the program memory are set to the program counter (PC).
However, when the interrupt level (ELEEVL) of the program status word (PSW) at reset by the BRK instruction
is 1 or lower, the contents of addresses 0004H and 0005H of the program memory are set in the program counter
(PC). For the BRK instruction, see “nX-U8/100 Core Instruction Manual”.
Description of Operation
Operation of System Reset Mode
3 – 3
ML610Q428/ML610Q429 User’s Manual
Chapter 3 Reset Function