ML610Q429-NNNTBZ03A7 Rohm Semiconductor, ML610Q429-NNNTBZ03A7 Datasheet - Page 216
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ML610Q429-NNNTBZ03A7
Manufacturer Part Number
ML610Q429-NNNTBZ03A7
Description
MCU 8BIT 48K FLASH 128-TQFP
Manufacturer
Rohm Semiconductor
Datasheets
1.ML610Q482P-NNNTB03A7.pdf
(20 pages)
2.ML610Q428-NNNTBZ03A7.pdf
(32 pages)
3.ML610Q428-NNNTBZ03A7.pdf
(434 pages)
Specifications of ML610Q429-NNNTBZ03A7
Core Processor
nX-U8/100
Core Size
8-Bit
Speed
4.2MHz
Connectivity
I²C, SSP, UART/USART
Peripherals
LCD, Melody Driver, POR, PWM, WDT
Number Of I /o
20
Program Memory Size
48KB (24K x 16)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.1 V ~ 3.6 V
Data Converters
A/D 2x12b, 2x24b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 70°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ML610Q429-NNNTBZ03A7
Manufacturer:
Rohm
Quantity:
900
Company:
Part Number:
ML610Q429-NNNTBZ03A7
Manufacturer:
Rohm Semiconductor
Quantity:
10 000
- ML610Q482P-NNNTB03A7 PDF datasheet
- ML610Q428-NNNTBZ03A7 PDF datasheet #2
- ML610Q428-NNNTBZ03A7 PDF datasheet #3
- Current page: 216 of 434
- Download datasheet (3Mb)
14.3.3
Figure 14-7 shows the operation waveforms of the SDA and SCL signals and the I20BB flag. Table 14-1 shows the
relationship between communication speeds and HSCLK clock counts.
Note
The HSCLK clock count is set so that the communication speed may be set to 100kbps/400kbps when HSCLK is 4
MHz. When the high-speed clock frequency is not 4 MHz, select an I2C0MOD communication speed reduction rate
and an FCON0 HSCLK frequency so that the communication speed may not exceed 100kbps/400kbps.
When the slave device uses the clock cycle function (handshake function) which holds the SCL signal at a “L” level,
the time t
φ: Period of high-speed clock (HSCLK)
Communication speed
Standard mode
Fast mode
100 kbps
400 kbps
SDA
SCL
I20BB
(I20SP)
CYC
Table 14-1 Relationship between Communication Speeds and HSCLK Clock Counts
Operation Waveforms
and time t
Figure 14-7 Operation Waveforms of SDA and SCL Signals and I20BB Flag
t
HD:STA
Start condition
LOW
t
LOW
10% reduction
20% reduction
30% reduction
10% reduction
20% reduction
30% reduction
t
are extended.
No reduction
No reduction
(I20DW1, 0)
CYC
reduction
Speed
tHD:DAT
t
40φ
44φ
48φ
52φ
10φ
11φ
12φ
13φ
CYC
t
HIGH
t
HD:STA
14 – 12
18φ
20φ
22φ
24φ
4φ
4φ
5φ
5φ
Restart condition
t
22φ
24φ
26φ
28φ
t
LOW
6φ
7φ
7φ
8φ
SU:STA
t
HD:DAT
4φ
4φ
4φ
4φ
2φ
2φ
2φ
2φ
ML610Q428/ML610Q429 User’s Manual
t
t
18φ
20φ
22φ
24φ
SU:DAT
HIGH
4φ
4φ
5φ
5φ
Chapter 14 I
t
SU:STA
22φ
24φ
26φ
28φ
6φ
7φ
7φ
8φ
t
t
SU:DAT
SU:STO
18φ
20φ
22φ
24φ
Stop condition
4φ
5φ
5φ
6φ
2
C Bus Interface
t
SU:STO
18φ
20φ
22φ
24φ
4φ
4φ
5φ
5φ
t
BUF
t
22φ
24φ
26φ
28φ
BUF
6φ
7φ
7φ
8φ
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