ML610Q429-NNNTBZ03A7 Rohm Semiconductor, ML610Q429-NNNTBZ03A7 Datasheet - Page 332
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ML610Q429-NNNTBZ03A7
Manufacturer Part Number
ML610Q429-NNNTBZ03A7
Description
MCU 8BIT 48K FLASH 128-TQFP
Manufacturer
Rohm Semiconductor
Datasheets
1.ML610Q482P-NNNTB03A7.pdf
(20 pages)
2.ML610Q428-NNNTBZ03A7.pdf
(32 pages)
3.ML610Q428-NNNTBZ03A7.pdf
(434 pages)
Specifications of ML610Q429-NNNTBZ03A7
Core Processor
nX-U8/100
Core Size
8-Bit
Speed
4.2MHz
Connectivity
I²C, SSP, UART/USART
Peripherals
LCD, Melody Driver, POR, PWM, WDT
Number Of I /o
20
Program Memory Size
48KB (24K x 16)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.1 V ~ 3.6 V
Data Converters
A/D 2x12b, 2x24b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 70°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ML610Q429-NNNTBZ03A7
Manufacturer:
Rohm
Quantity:
900
Company:
Part Number:
ML610Q429-NNNTBZ03A7
Manufacturer:
Rohm Semiconductor
Quantity:
10 000
- ML610Q482P-NNNTB03A7 PDF datasheet
- ML610Q428-NNNTBZ03A7 PDF datasheet #2
- ML610Q428-NNNTBZ03A7 PDF datasheet #3
- Current page: 332 of 434
- Download datasheet (3Mb)
24.2.5
• DADM1, DADM0 (bits 1-0)
• DASN (bit 2)
Address: 0F0F3H
Access: R/W
Access size: 8 bits
Initial value: 00H
DSPMOD1 is a special register (SFR) to control the display mode of the LCD drivers.
Use DSPMOD1 to select a type of display register segment map and determine to use or unuse the programmable display
allocation function (display allocation RAM).
[Description of Bits]
Note:
When using the programmable display allocation, select type 3 for the display register segment map. Oki semiconductor
LCD Tool only generates table data can be used for the type 3.
DSPMOD1
Initial value
DADM1 and DADM0 are used to select a type of display register segment map. Three types are available; type 1, type
2, and type 3 . See section 24.2.9 and section 24.3.2.
The DASN bit is used to control the operation of the display allocation function.
Setting the DASN bit to “1” enables the display allocation function.
R/W
DADM1
DASN
0
0
1
0
1
Display Mode Register 1 (DSPMOD1)
Not use Programmable display allocation (initial value)
Use Programmable display allocation
DADM0
R/W
⎯
7
0
0
1
*
Display register segment map type 1 (initial value)
Display register segment map type 2
Display register segment map type 3
R/W
⎯
0
6
R/W
⎯
5
0
Description
R/W
⎯
4
0
24 – 14
Description
R/W
⎯
3
0
ML610Q428/ML610Q429 User’s Manual
DASN
R/W
2
0
DADM1
R/W
Chapter 24 LCD Drivers
0
1
DADM0
R/W
0
0
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