ML610Q429-NNNTBZ03A7 Rohm Semiconductor, ML610Q429-NNNTBZ03A7 Datasheet
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ML610Q429-NNNTBZ03A7 Summary of contents
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... ML610Q428/ML610Q429 User’s Manual FEUL610Q428-01 Issue Date: Dec 3, 2010 ...
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NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application ...
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... User’s Manual Description on the on-chip debug tool uEASE. uEASE connection Manual Description about the connection between uEASE and FWuEASE Flash Writer Host Program User’s Manual Description on the Flash Writer host program. Preface . compiler . . DTU8 . IDEU8 ML610Q428/ML610Q429 . nX-U8/100 Core . ...
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Classification Notation ♦ Numeric value xxh, xxH xxb ♦ Unit word, W byte, B nibble, N maga-, M kilo-, K kilo-, k milli-, m micro-, µ nano-, n second, s (lower case) ♦ Terminology “H” level, “1” level “L” level, ...
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... Pad Coordinates of ML610Q429 Chip .......................................................................................... 1-11 1.3.2 List of Pins........................................................................................................................................ 1-12 1.3.3 Description of Pins............................................................................................................................ 1-16 1.3.4 Termination of Unused Pins ............................................................................................................. 1-20 1.3.5 The main difference points of ML610Q428 and ML610Q429......................................................... 1-20 Chapter 2 2. CPU ................................................................................................................................................................ 2-1 2.1 Overview..................................................................................................................................................... 2-1 2.2 Program Memory Space ............................................................................................................................. 2-1 2.3 Data Memory Space ...
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... Description of Operation............................................................................................................................. 6-6 6.3.1 Low-Speed Clock ............................................................................................................................... 6-6 6.3.1.1 Low-Speed Clock Generation Circuit ............................................................................................. 6-6 6.3.1.2 Operation of Low-Speed Clock Generation Circuit ........................................................................ 6-7 6.3.2 High-Speed Clock............................................................................................................................... 6-8 6.3.2.1 500 kHz RC Oscillation................................................................................................................... 6-8 6.3.2.2 Crystal/Ceramic Oscillation Mode .................................................................................................. 6-9 ML610Q428/ML610Q429 User’s Manual Contents – 2 Contents ...
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... Timer 0 Control Register 0 (TM0CON0) ........................................................................................... 9-7 9.2.7 Timer 1 Control Register 0 (TM1CON0) ........................................................................................... 9-9 9.2.8 Timer 0 Control Register 1 (TM0CON1) ......................................................................................... 9-10 9.2.9 Timer 1 Control Register 1 (TM1CON1) ......................................................................................... 9-11 9.3 Description of Operation........................................................................................................................... 9-12 Chapter 10 10. PWM............................................................................................................................................................. 10-1 10.1 Overview................................................................................................................................................... 10-1 ML610Q428/ML610Q429 User’s Manual Contents – 3 Contents ...
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... Serial Port Mode Register 0 (SIO0MOD0)....................................................................................... 12-6 12.2.5 Serial Port Mode Register 1 (SIO0MOD1)....................................................................................... 12-7 12.3 Description of Operation........................................................................................................................... 12-8 12.3.1 Transmit Operation ........................................................................................................................... 12-8 12.3.2 Receive Operation............................................................................................................................. 12-9 12.3.3 Transmit/Receive Operation ........................................................................................................... 12-10 12.4 Specifying port registers ......................................................................................................................... 12-11 ML610Q428/ML610Q429 User’s Manual Contents – 4 Contents ...
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... Data Receive Mode ....................................................................................................................... 14-9 14.3.1.6 Control Register Setting Wait State............................................................................................... 14-9 14.3.1.7 Stop Condition............................................................................................................................... 14-9 14.3.2 Communication Operation Timing ................................................................................................. 14-10 14.3.3 Operation Waveforms..................................................................................................................... 14-12 14.4 Description of Operation......................................................................................................................... 14-13 14.4.1 Functioning P41(SCL) and P40(SDA) as the I2C .......................................................................... 14-13 ML610Q428/ML610Q429 User’s Manual Contents – 5 Contents ...
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... List of Pins........................................................................................................................................ 18-1 18.2 Description of Registers............................................................................................................................ 18-2 18.2.1 List of Registers ................................................................................................................................ 18-2 18.2.2 Port 2 Data Register (P2D) ............................................................................................................... 18-3 18.2.3 Port 2 control registers 0, 1 (P2CON0, P2CON1) ............................................................................ 18-4 18.2.4 Port 2 Mode Register 0, 1 (P2MOD0, P2MOD1 )............................................................................ 18-5 ML610Q428/ML610Q429 User’s Manual Contents – 6 Contents ...
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... Port A Direction Register (PADIR) .................................................................................................. 21-4 21.2.4 Port A Control Registers 0, 1 (PACON0, PACON1) ....................................................................... 21-5 21.3 Description of Operation........................................................................................................................... 21-7 21.3.1 Input/Output Port Functions ............................................................................................................. 21-7 Chapter 22 22. Melody Driver .............................................................................................................................................. 22-1 22.1 Overview................................................................................................................................................... 22-1 22.1.1 Features............................................................................................................................................. 22-1 ML610Q428/ML610Q429 User’s Manual Contents – 7 Contents ...
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... Display Mode Register 0 (DSPMOD0) .......................................................................................... 24-12 24.2.5 Display Mode Register 1 (DSPMOD1) .......................................................................................... 24-14 24.2.6 Display Control Register (DSPCON) ............................................................................................. 24-15 24.2.7 Display Allocation Register A (DS0C0A to DS63C7A) ................................................................ 24-16 24.2.8 Display Allocation Register B (DS0C0B to DS63C7B) ................................................................. 24-18 24.2.9 Display Registers (DSPR00 to DSPRFE) ....................................................................................... 24-20 ML610Q428/ML610Q429 User’s Manual Contents – 8 Contents ...
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... Method of Connecting to On-Chip Debug Emulator ................................................................................ 27-1 27.3 Flash Memory Rewrite Function .............................................................................................................. 27-2 Appendixes Appendix A Registers......................................................................................................................................... A-1 Appendix B Package Dimensions........................................................................................................................B-1 Appendix C Electrical Characteristics .................................................................................................................C-1 Appendix D Application Circuit Example.......................................................................................................... D-1 Appendix E Check List........................................................................................................................................E-1 Revision History Revision History .....................................................................................................................................................R-1 ML610Q428/ML610Q429 User’s Manual Contents – 9 Contents ...
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Chapter 1 Overview ...
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... Watchdog timer − Non-maskable interrupt and reset − Free running − Overflow period: 4 types selectable (125ms, 500ms, 2s, and 8s) • Timers − 8 bits × 2 channels (16-bit configuration available) • 1 kHz timer − 10 Hz/1 Hz interrupt function ML610Q428/ML610Q429 User’s Manual 1 – 1 Chapter 1 Overview ...
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... Non-maskable interrupt input port × 1 channel − Input-only port × 10 channels (including secondary functions) − Output-only port × 3 channels (including secondary functions) − Input/output port ML610Q428: 14 channels (including secondary functions) ML610Q429: 20 channels (including secondary functions) ML610Q428/ML610Q429 User’s Manual 1 – 2 Chapter 1 Overview ...
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... Dot matrix can be supported. ML610Q428: 1392 dots max. (58 seg × 24 com), 1/1 to 1/24 duty ML610Q429: 512 dots max. (64 seg × 8 com) , 1/1 to 1/8 duty − 1/3 or 1/4 bias (built-in bias generation circuit) − Frame frequency selecable (approx. 32Hz, 64 Hz, 73 Hz, 85 Hz, and 102 Hz) − ...
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... INT 8 TBC INT 1 INT 1kHzTC 1 INT 2 8bit Timer ×2 Display Allocation RAM 1KByte Display RAM 192Byte Figure 1-1 Block Diagram of ML610Q428 1 – 4 ML610Q428/ML610Q429 User’s Manual Chapter 1 Overview PC Program BUS Memory V (Flash) 48Kbyte INT 1 SCK0* SSIO SIN0* SOUT0* INT 1 RXD0* UART ...
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... INT 1 WDT INT 8 TBC INT 1 INT 1kHzTC 1 INT 2 8bit Timer ×2 Display Allocation RAM 1KByte Display RAM 192Byte Figure 1-2 Block Diagram of ML610Q429 1 – 5 ML610Q428/ML610Q429 User’s Manual Chapter 1 Overview PC Program BUS Memory V (Flash) PP 48Kbyte INT 1 SCK0* SSIO SIN0* SOUT0* INT ...
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... P43 122 V 123 L1 V 124 L2 V 125 L3 V 126 L4 C1 127 C2 128 128pin 1pin (NC): No Connection Figure 1-3 Pin Layout of ML610Q428 Package ML610Q428/ML610Q429 User’s Manual ML610Q428 1 – 6 Chapter 1 Overview 65pin 64pin 64 SEG42 63 SEG41 62 SEG40 61 SEG39 60 SEG38 59 SEG37 58 SEG36 57 SEG35 56 ...
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... P43 122 V 123 L1 V 124 L2 V 125 L3 V 126 L4 C1 127 C2 128 128pin 1pin (NC): No Connection Figure 1-4 Pin Layout of ML610Q429 Package ML610Q428/ML610Q429 User’s Manual ML610Q429 1 – 7 Chapter 1 Overview 65pin 64pin 64 SEG42 63 SEG41 62 SEG40 61 SEG39 60 SEG38 59 SEG37 58 SEG36 57 SEG35 ...
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... A chip angle can be checked by the distinguishing mark of three figures. Device Name "428" 428 Chip size: PAD count: Minimum PAD pitch: PAD aperture: Chip thickness: Voltage of the rear side of chip: V Figure 1-5 Dimensions of ML610Q428 Chip 1 – 8 ML610Q428/ML610Q429 User’s Manual Chapter 1 Overview ...
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... A chip angle can be checked by the distinguishing mark of three figures. Chip size: PAD count: Minimum PAD pitch: PAD aperture: Chip thickness: Voltage of the rear side of chip: V Figure 1-6 Dimensions of ML610Q429 Chip 1 – 9 ML610Q428/ML610Q429 User’s Manual Chapter 1 Overview 2.99 mm × 3.11 mm 125 pins 80 μm 70 μ ...
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... COM11 -205 -600 82 COM12 -285 -520 83 COM13 -365 -440 84 COM14 -465 -360 85 COM15 -545 -280 86 COM16 -625 1 – 10 ML610Q428/ML610Q429 User’s Manual Chapter 1 Overview Chip Center: X=0,Y=0 Y PAD Pad X (μm) No. Name (μm) -200 COM17 87 -705 -120 COM18 88 -785 -40 89 COM19 -865 ...
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... SEG15 1389 36 SEG16 1389 37 SEG17 1389 38 SEG18 1389 39 SEG19 1389 40 SEG20 1389 41 SEG21 1389 42 SEG22 1389 43 SEG23 1389 Table 1-2 Pad Coordinates of ML610Q429 Y PAD Pad (μm) No. Name (μm) -1449 44 SEG24 1389 -1449 45 SEG25 1389 -1449 46 SEG26 1389 -1449 47 SEG27 1389 -1449 48 ...
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... ML610Q428/ML610Q429 User’s Manual Chapter 1 Overview Tertiary function Function Pin name I/O ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ...
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... ML610Q428/ML610Q429 User’s Manual Chapter 1 Overview Tertiary function Function Pin name I/O ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ...
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... ML610Q428/ML610Q429 User’s Manual Chapter 1 Overview Tertiary function Function Pin name I/O ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ...
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... ML610Q428/ML610Q429 User’s Manual Chapter 1 Overview Tertiary function Function Pin name I/O ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ...
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... General-purpose input port. P04-P07 I Since these pins have secondary functions, the pins cannot be used as a port when the secondary functions are used. These pins are for the ML610Q429, but are not provided in the ML610Q428. General-purpose input port. P10-P11 I Since these pins have secondary functions, the pins cannot be used as a port when the secondary functions are used ...
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... P22 pin. LED drive Nch open drain output pins to drive LED. LED0-2 O Description 2 C, externally connect a pull-up resistor externally connect a pull-up resistor. 1 – 17 ML610Q428/ML610Q429 User’s Manual Chapter 1 Overview Primary/ Secondary/ Tertiary Secondary Primary/Se condary Secondary Secondary Tertiary Tertiary ...
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... ML610Q429. Segment output pin. SEG0-57 O Segment output pins. SEG58-63 O These pins are for the ML610Q429, but are not provided in the ML610Q428. LCD driver power supply Power supply pins for LCD bias (internally generated). Capacitors Ca, Cb, V — L1 Cc, and Cd (see measuring circuit 1) are connected between V V — ...
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... It is recommended to set the unused input ports and input/output ports to the inputs with pull-down resistors/pull-up resistors or the output mode since the supply current may become excessively large if the pins are left open in the high impedance input setting. 1.3.5 The main difference points of ML610Q428 and ML610Q429 Table 1-4 Function PORT0 ...
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CPU and Memory Space Chapter 2 ...
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... Vector Table Area or Program Code ROM Window Area Program Code or ROM Window Area 0:BC00H 0:BDFFH 0:BE00H Test Data Area 0:BFFFH 8bit 2 – 1 ML610Q428/ML610Q429 User’s Manual Chapter 2 CPU and Memory Space Test Data Area Write-able Test Data Area Non write-able 8bit ...
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... ROM Window Area 8:0BBFFH 8:0BC00H Test Data Area 8:0BFFFH 8:0C000H Unused Area RAM Area 3KByte Unused Area SFR Area 8:0FFFFH 8bit 2 – 2 ML610Q428/ML610Q429 User’s Manual Chapter 2 CPU and Memory Space Segment 8 ROM Reference Area Test Data Area Unused Area 8bit ...
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... Description of Registers 2.6.1 List of Registers Address Name 0F000H Data segment register ML610Q428/ML610Q429 User’s Manual Chapter 2 CPU and Memory Space Symbol (Byte) Symbol (Word) ⎯ DSR 2 – 3 R/W Size Initial value R/W 8 00H ...
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... Instruction Manual”. [Description of Bits] • DSR3-DSR0 (bits 3-0) DSR3 DSR2 DSR1 ⎯ ⎯ R/W R DSR0 0 0 Data segment 0 (initial value Prohibited Data segment Prohibited – 4 ML610Q428/ML610Q429 User’s Manual Chapter 2 CPU and Memory Space DSR3 DSR2 DSR1 R/W R/W R Description 0 DSR0 R/W 0 ...
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Chapter 3 Reset Function ...
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... Low-speed Oscillation stop detect reset WDT reset RSTAT: Reset status register Figure 3-1 Configuration of Reset Generation Circuit 3.1.3 List of Pin Pin name I/O RESET_N I Reset input pin ML610Q428/ML610Q429 User’s Manual Chapter 3 Reset Function RSTAT Description 3 – 1 Reset signal Data bus ...
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... The WSDTR is a flag that indicates that the watchdog timer reset is generated. This bit is set to “1” when the reset by overflow of the watchdog timer is generated. WDTR 0 Watchdog timer reset not occurred 1 Watchdog timer reset occurred Note: No flag is provided that indicates the occurrence of reset by the RESET_N pin. ML610Q428/ML610Q429 User’s Manual Symbol (Byte) Symbol (Word) RSTAT ― ― ...
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... In system reset mode, the contents of data memory and those of any SFR whose initial value is undefined are not initialized and are undefined. Initialize them by software. In system reset mode by the BRK instruction, no special function register (SFR) that has a fixed initial value is initialized either. Therefore initialize such an SFR by software. ML610Q428/ML610Q429 User’s Manual Chapter 3 Reset Function 3 – 3 ...
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MCU Control Function Chapter 4 ...
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... System reset Reset Figure 4-1 Operating State Transition Diagram Release of reset mode Reset or BRK instruction STP = “1” Reset External interrupt STOP mode 4 – 1 ML610Q428/ML610Q429 User’s Manual Chapter 4 MCU Control Function Program run mode HLT = “1” Interrupt HALT mode ...
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... Block control register 0 0F028H 0F029H Block control register 1 0F02AH Block control register 2 Block control register 3 0F02BH Block control register 4 0F02CH ML610Q428/ML610Q429 User’s Manual Chapter 4 MCU Control Function Symbol (Byte) Symbol (Word) ⎯ STPACP ⎯ SBYCON ⎯ BLKCON0 ⎯ BLKCON1 ⎯ ...
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... Note: The STOP code acceptor can not be enabled on the condition of that both any interrupt enable flag and the corresponding interrupt request flag are “1”(An interrupt request occurrence with resetting MIE flag will have the condition). ML610Q428/ML610Q429 User’s Manual ― ...
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... When a maskable interrupt source (interrupt with enable bit) occurs while the MIE flag of the program status word (PSW) in the nX-U8/100 core is “0”, the STOP mode and the HALT mode are simply released and interrupt processing is not performed. Refer to the “nX-U8/100 Core Instruction Manual” for details of PSW. ML610Q428/ML610Q429 User’s Manual ― ...
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... Ensure the bits are reset to “0” before using the peripherals to enable the operation. See Chapter 9, “Timers” for detail about operation of Timer 0 and Timer 1. ML610Q428/ML610Q429 User’s Manual ― ...
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... Ensure the bits are reset to “0” before using the peripherals to enable the operation. See Chapter 8, “1kHz Timer” for detail about operation of 1kHz Timer. See Chapter 10, “PWM” for detail about operation of PWM. ML610Q428/ML610Q429 User’s Manual ― ...
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... Ensure the bits are reset to “0” before using the peripherals to enable the operation. See Chapter 14, “I2C Bus Interface” for detail about operation of I2C Bus Interface. See Chapter 13, “UART” for detail about operation of UART. See Chapter 12, “Synchronous Serial Port” for detail about operation of SSIO. ML610Q428/ML610Q429 User’s Manual ― ...
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... Ensure the bits are reset to “0” before using the peripherals to enable the operation. See Chapter 22, “Melody Driver” for detail about operation of Melody/Buzzer. ML610Q428/ML610Q429 User’s Manual ― ...
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... The DRAD bit is used to control RC type A/D converter operation. When the DRAD bit is set to “1”, the circuits related to RC type A/D converter are reset and turned off. DRAD Enable operating RC type A/D converter (initial value Disable operating RC type A/D converter ML610Q428/ML610Q429 User’s Manual DBLD DXTSP ― ...
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... See Chapter 25, “Battery Level Detector” for detail about operation of BLD. See Chapter 3, “Reset Function” for detail about operation of 32kHz oscillation stop detector. See Chapter 23, “RC Oscillation Type A/D Converter” for detail about operation of RC oscillation type A/D converter. ML610Q428/ML610Q429 User’s Manual Chapter 4 MCU Control Function 4 – 10 ...
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... Since up to two instructions are executed during the period between HALT mode release and a transition to interrupt processing, place two NOP instructions next to the instruction that sets the HLT bit to “1”. ML610Q428/ML610Q429 User’s Manual Chapter 4 MCU Control Function HALT mode Program operating mode 4 – ...
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... Oscillation waveform waveform HSCLK HSCLK waveform SBYCON.STP bit Interrupt request Program operating mode Figure 4-3 Operation Waveforms in STOP Mode When CPU Operates with Low-Speed Clock ML610Q428/ML610Q429 User’s Manual Chapter 4 MCU Control Function Oscillation waveform Hiz Low-speed oscillation T 8192-pulse count XTL STOP mode 4 – ...
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... STOP mode release and a transition to interrupt processing. Therefore, place two NOP instructions next to the instruction that set the STP bit to “1”. HSCLK waveform Hiz STOP mode 4 – 13 ML610Q428/ML610Q429 User’s Manual Chapter 4 MCU Control Function High-speed oscillation waveform T /T XTH ...
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... STP/HLT bit to “1”. The program operation does not go to the 1 interrupt routine. After the mode is returned from the STOP/HALT mode, program 1 operation restarts from the instruction following the instruction that sets the STP/HLT bit to “1”, then goes to the interrupt routine. 4 – 14 ML610Q428/ML610Q429 User’s Manual Chapter 4 MCU Control Function ...
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... BLKCON4 register controls(disables/enables) operation of LCD driver, Battery Level Detector, 32kHz oscillation stop detector and RC type A/D converter. Note: See the each chapter for detail about the opeation of each peripheral and relevant notes. ML610Q428/ML610Q429 User’s Manual Chapter 4 MCU Control Function 4 – 15 ...
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Chapter 5 Interrupts (INTs) ...
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... Features • 2 non-maskable interrupt sources (Internal source: 1, External source: 1) • 27 maskable interrupt sources (Internal sources: 19, External sources: 8) • Software interrupt (SWI): 64 sources max. • External interrupts allow edge selection and sampling selection. ML610Q428/ML610Q429 User’s Manual Chapter 5 Interrupts (INTs) 5 – 1 ...
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... Interrupt request register 1 0F01AH Interrupt request register 2 0F01BH Interrupt request register 3 0F01CH Interrupt request register 4 0F01EH Interrupt request register 6 0F01FH Interrupt request register 7 ML610Q428/ML610Q429 User’s Manual Chapter 5 Interrupts (INTs) Symbol (Byte) Symbol (Word) ⎯ IE1 ⎯ IE2 ⎯ IE3 ⎯ ...
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... EP03 is the enable flag for the input port P03 pin interrupt (P03INT). EP03 0 Disabled (initial value) 1 Enabled • EP04 (bit 4) EP04 is the enable flag for the input port P04 pin interrupt (P04INT). EP04 0 Disabled (initial value) 1 Enabled ML610Q428/ML610Q429 User’s Manual EP05 EP04 EP03 R/W R/W R ...
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... EP06 is the enable flag for the input port P06 pin interrupt (P06INT). EP06 0 Disabled (initial value) 1 Enabled • EP07 (bit 7) EP07 is the enable flag for the input port P07 pin interrupt (P07INT). EP07 0 Disabled (initial value) 1 Enabled ML610Q428/ML610Q429 User’s Manual Description Description Description 5 – 4 Chapter 5 Interrupts (INTs) ...
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... ESIO0 is the enable flag for the synchronous serial port 0 interrupt (SIO0INT). ESIO0 0 Disabled (initial value) 1 Enabled • EI2C0 (bit 7) EI2C0 is the enable flag for the I2C bus 0 interrupt (I2C0INT). EI2C0 0 Disabled (initial value) 1 Enabled ML610Q428/ML610Q429 User’s Manual ⎯ ⎯ ⎯ R/W R/W R ...
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... ETM0 is the enable flag for the timer 0 interrupt (TM0INT). ETM0 0 Disabled (initial value) 1 Enabled • ETM1 (bit 1) ETM1 is the enable flag for the timer 1 interrupt (TM1INT). ETM1 0 Disabled (initial value) 1 Enabled ML610Q428/ML610Q429 User’s Manual ⎯ ⎯ ⎯ R/W R/W R Description Description 5 – ...
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... EMD0 is the enable flag for the melody 0 interrupt (MD0INT). EMD0 0 Disabled (initial value) 1 Enabled • ERAD (bit 5) ERAD is the enable flag for the RC oscillation type A/D converter interrupt (RADINT). ERAD 0 Disabled (initial value) 1 Enabled ML610Q428/ML610Q429 User’s Manual ⎯ ⎯ ERAD R/W R/W R ...
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... ET1K is the enable flag for the 1 kHz timer interrupt (T1KINT). ET1K 0 Disabled (initial value) 1 Enabled • E128H (bit 5) E128H is the enable flag for the time base counter 128 Hz interrupt (T128HINT). E128H 0 Disabled (initial value) 1 Enabled ML610Q428/ML610Q429 User’s Manual ⎯ E128H ET1K R/W R/W R ...
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... E64H is the enable flag for the time base counter 64 Hz interrupt (T64HINT). E64H 0 Disabled (initial value) 1 Enabled • E32H (bit 7) E32H is the enable flag for the time base counter 32 Hz interrupt (T32HINT). E32H 0 Disabled (initial value) 1 Enabled ML610Q428/ML610Q429 User’s Manual Description Description 5 – 9 Chapter 5 Interrupts (INTs) ...
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... E2H is the enable flag for the time base counter 2 Hz interrupt (T2HINT). E2H 0 Disabled (initial value) 1 Enabled • E1H (bit 4) E1H is the enable flag for the time base counter 1 Hz interrupt (T1HINT). E1H 0 Disabled (initial value) 1 Enabled ML610Q428/ML610Q429 User’s Manual ⎯ E1H E2H R/W R/W R ...
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... QNMI is the request flag for the NMI interrupt (NMINT). QNMI 0 No request (initial value) 1 Request Note: When an interrupt is generated by the write instruction to the interrupt request register (IRQ0), the interrupt shift cycle starts after the next 1 instruction is executed. ML610Q428/ML610Q429 User’s Manual ⎯ ⎯ ⎯ R/W R/W ...
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... QP03 is the request flag for the input port P03 pin interrupt (P03INT). QP03 0 No request (initial value) 1 Request • QP04 (bit 4) QP04 is the request flag for the input port P04 pin interrupt (P04INT). QP04 0 No request (initial value) 1 Request ML610Q428/ML610Q429 User’s Manual QP05 QP04 QP03 R/W R/W R ...
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... No request (initial value) 1 Request Note: When an interrupt is generated by the write instruction to the interrupt request register (IRQ1 the interrupt enable register (IE1), the interrupt shift cycle starts after the next 1 instruction is executed. ML610Q428/ML610Q429 User’s Manual Description Description Description 5 – 13 Chapter 5 Interrupts (INTs) ...
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... QI2C0 0 No request (initial value) 1 Request Note: When an interrupt is generated by the write instruction to the interrupt request register (IRQ2 the interrupt enable register (IE2), the interrupt shift cycle starts after the next 1 instruction is executed. ML610Q428/ML610Q429 User’s Manual ⎯ ⎯ ⎯ R/W ...
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... QTM1 0 No request (initial value) 1 Request Note: When an interrupt is generated by the write instruction to the interrupt request register (IRQ3 the interrupt enable register (IE3), the interrupt shift cycle starts after the next 1 instruction is executed. ML610Q428/ML610Q429 User’s Manual ⎯ ⎯ ⎯ R/W ...
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... QRAD 0 No request (initial value) 1 Request Note: When an interrupt is generated by the write instruction to the interrupt request register (IRQ4 the interrupt enable register (IE4), the interrupt shift cycle starts after the next 1 instruction is executed. ML610Q428/ML610Q429 User’s Manual ⎯ ⎯ QRAD R/W ...
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... QT1K is the request flag for the 1 kHz timer interrupt (T1KINT). QT1K 0 No request (initial value) 1 Request • Q128H (bit 5) Q128H is the request flag for the time base counter 128 Hz interrupt (T128HINT). Q128H 0 No request (initial value) 1 Request ML610Q428/ML610Q429 User’s Manual ⎯ Q128H QT1K R/W R/W R ...
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... No request (initial value) 1 Request Note: When an interrupt is generated by the write instruction to the interrupt request register (IRQ6 the interrupt enable register (IE6), the interrupt shift cycle starts after the next 1 instruction is executed. ML610Q428/ML610Q429 User’s Manual Description Description 5 – 18 Chapter 5 Interrupts (INTs) ...
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... Q4H is the request flag for the time base counter 4 Hz interrupt (T4HINT). Q4H 0 No request (initial value) 1 Request • Q2H (bit 3) Q2H is the request flag for the time base counter 2 Hz interrupt (T2HINT). Q2H 0 No request (initial value) 1 Request ML610Q428/ML610Q429 User’s Manual ⎯ Q1H Q2H R/W R/W R ...
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... No request (initial value) 1 Request Note: When an interrupt is generated by the instruction to write to the interrupt request register (IRQ7 the interrupt enable register (IE7), the the interrupt shift cycle starts after the next 1 instruction is executed. ML610Q428/ML610Q429 User’s Manual Description 5 – 20 Chapter 5 Interrupts (INTs) ...
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... Table 5-1 Interrupt Sources Interrupt source WDTINT SIO0INT I2C0INT MD0INT RADINT PW0INT PW1INT PW2INT T128HINT T64HINT T32HINT T16HINT 5 – 21 ML610Q428/ML610Q429 User’s Manual Chapter 5 Interrupts (INTs) Symbol Vector table address 0008H NMINT 000AH P00INT 0010H P01INT 0012H P02INT 0014H P03INT 0016H ...
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... Set the MIE flag to “0”. (5) Set the ELEVEL field to “1”. (6) Load the interrupt start address into PC. Reference: For the MIE flag, Program Counter (PC), CSR, PSW, and ELEVEL, see “nX-U8/100 Core Instruction Manual”. ML610Q428/ML610Q429 User’s Manual Chapter 5 Interrupts (INTs) 5 – 22 ...
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... Example of description: State A-1-1 Intrpt_A-1-1; ; A-1-1 state DI ; Disable interrupt : : : RTI ; Return PC from ELR ; Return PSW form EPSW ; End ML610Q428/ML610Q429 User’s Manual Chapter 5 Interrupts (INTs) Example of description: State A-1-2 Intrpt_A-1-2; ; Start ; Save ELR and EPSW at the PUSH ELR, EPSW beginning EI ; Enable interrupt : : ...
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... POP PC, PSW Start ; Save ELR, EPSW the beginning ; Enable interrupt ; Call subroutine Sub_1 ; Return PC from the stack ; Return PSW from the stack ; Return LR from the stack ; End 5 – 24 ML610Q428/ML610Q429 User’s Manual Chapter 5 Interrupts (INTs) Sub_1 Disable interrupt : : : RT ; Return PC from LR ; End of subroutine ...
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... BL Sub_1 ; Call subroutine Sub_1 : POP PC，PSW，LR ; Return PC from the stack ; Return PSW from the stack ; Return LR from the stack ; End ML610Q428/ML610Q429 User’s Manual Chapter 5 Interrupts (INTs) Example of description: B-2-1 Intrpt_B-2-1: ; Start PUSH ELR，EPSW ; Save ELR, EPSW at the beginning ...
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... Between the DSR prefix instruction and the next instruction When the interrupt conditions are satisfied in this section, an interrupt is generated immediately after execution of the instruction following the DSR prefix instruction. Reference: For the DSR prefix instruction, see “nX-U8/100 Core Instruction Manual”. ML610Q428/ML610Q429 User’s Manual Chapter 5 Interrupts (INTs) 5 – 26 ...
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Clock Generation Circuit Chapter 6 ...
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... This LSI starts operation with a clock generated by dividing the 500 kHz RC oscillation frequency by 8 after power- system reset. At initialization by software, set the FCON0 or FCON1 register to switch the clock to a required one. Operation of this LSI is not guaranteed under a condition where a low-speed clock is not supplied. ML610Q428/ML610Q429 User’s Manual Divide ratio OSCLK ...
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... Description of Registers 6.2.1 List of Registers Address Frequency control register 0 0F002H 0F003H Frequency control register 1 Description Name Symbol (Byte) FCON0 FCON1 6 – 2 ML610Q428/ML610Q429 User’s Manual Chapter 6 Clock Generation Circuit Symbol (Word) R/W Size R/W 8/16 FCON R/W 8 Initial value 33H 03H ...
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... OSCLK (1/2OSCLK in built-in PLL oscillation mode) 1/2OSCLK 1/4OSCLK 1/8OSCLK (initial value) OSCM0 0 500kHz RC oscillation mode (initial value) 1 Crystal/ceramic oscillation mode 0 Built-in PLL oscillation mode 1 External clock input mode X 2MHz RC oscillation mode 6 – 3 ML610Q428/ML610Q429 User’s Manual Chapter 6 Clock Generation Circuit OSCM0 SYSC1 R/W R Description 0 SYSC0 R/W ...
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... When built-in PLL (about 8.192 MHz) oscillation mode is selected (OSCM2 = “0”, OSCM1 = “1”, OSCM0 = “0”), 1/2OSCLK (about 4.096 MHz) is output as HSCLK even if OSCLK (SYSC0 = “0”, SYSC1 = “1”) is selected. Description OSCLK 1/2OSCLK 1/4OSCLK 1/8OSCLK (initial value) 6 – 4 ML610Q428/ML610Q429 User’s Manual Chapter 6 Clock Generation Circuit ...
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... When the LPLL bit is set to “0”, this indicates that the PLL oscillation is inactive or the PLL oscillation frequency is not within 8.192 MHz±2.5%. LPLL is a read-only bit. LPLL Disables the use of PLL oscillation (initial value) 0 Enables the use of PLL oscillation 1 ML610Q428/ML610Q429 User’s Manual ⎯ ⎯ ⎯ R/W ...
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... Note that oscillation may stop due to condensation. V DDX Control Circuit – 6 ML610Q428/ML610Q429 User’s Manual Chapter 6 Clock Generation Circuit and required STOP mode Low-speed clock (LSCLK) 2× clock 2× low-speed clock circuit (LSCLK×2) ENMLT ...
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... Low-speed clock oscillation waveform Low-speed oscillation Count: 4096 Low-speed oscillation Count: 8192 LSCLK waveform Start of LSCLK supply 6 – 7 ML610Q428/ML610Q429 User’s Manual Chapter 6 Clock Generation Circuit T : Oscillation start time XTL Low-speed clock oscillation waveform Low-speed oscillation Count: 4096 Low-speed oscillation Count: 8192 ...
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... The 500kHz-RC oscillation mode is allowed within the range of V − After system reset mode is released, supply of OSCLK starts after the RC oscillation clock pulse count reaches 8192. After release of a STOP mode, supply of OSCLK starts. ML610Q428/ML610Q429 User’s Manual Chapter 6 Clock Generation Circuit STOP mode ...
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... The crystal or the ceramic resonator connected to the P10/OSC0 and P11/OSC1 pins should not exceed the guaranteed maximum operation frequency of 4.2 MHz of the system clock (SYSCLK) of this LSI range of 1 3.6 V. Select a frequency DD 6 – 9 ML610Q428/ML610Q429 User’s Manual Chapter 6 Clock Generation Circuit STOP mode ENOSC (Enables oscillation) OSCLK Count: 4096 (High-speed oscillation clock) ...
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... V to 3.6 V. Select a frequency according and lower than V to the P10/OSC0 pin input – 10 ML610Q428/ML610Q429 User’s Manual Chapter 6 Clock Generation Circuit OSCLK (High-speed oscillation clock) STOP mode ENOSC (Enables oscillation) High-speed oscillation clock (OSCLK) and between the P10/OSC0 pin and V ...
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... Figure 6-8 Circuit Configuration in 2MHz RC Oscillation Mode Notes: − The 2MHz RC osillation mode can be used within a V the operation voltage range by using the power supply voltage detection circuit (BLD). ML610Q428/ML610Q429 User’s Manual STOP mode ENOSC (Enables oscillation) Count: 2048 OSCLK (High-speed oscillation clock) range of 1 ...
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... High-speed oscillation clock waveform High-speed oscillation Count: 8192 CPU start / each mode and the oscillation stabilization period of the RC XTH PLL 6 – 12 ML610Q428/ML610Q429 User’s Manual Chapter 6 Clock Generation Circuit ) and the oscillation stabilization time RC HSCLK waveform SYSCLK waveform / each mode and the oscillation RC XTH ...
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... High-speed/PLL oscillation start time XTH PLL High-speed oscillation waveform High-speed oscillation Count: 4096 HSCLK waveform Low-speed clock oscillation waveform Generation of external 6 – 13 ML610Q428/ML610Q429 User’s Manual Chapter 6 Clock Generation Circuit High-speed/PLL oscillation start time XTH PLL High-speed oscillation waveform High-speed oscillation Count: 4096 ...
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... STOP mode, the CPU becomes inactive until LSCLK starts clock supply to the peripheral circuits. Therefore recommended to switch to LSCLK after confirming that the LSCLK is oscillating by checking that the time base counter interrupt request bit (Q128H) is “1”. ML610Q428/ML610Q429 User’s Manual System clock switching (High-speed clock→Low-speed clock) Stop of high-speed oscillation ...
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... WAIT @PLL oscillation mode ) WAIT WAIT @Internal clock input mode WAIT MHz RC oscillation mode WAIT System clock switching (Low-speed clock→High-speed clock) 6 – 15 ML610Q428/ML610Q429 User’s Manual Chapter 6 Clock Generation Circuit is 1.8V or higher by using BLD 1.3V or higher for ...
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... P21(Port2 output-only port, does not have an register to select the data direction(input or output). P2MOD register (Address: 0F214H P2CON1 register (Address: 0F213H P2CON0 register (Address: 0F212H P2D register (Address: 0F210H – 16 ML610Q428/ML610Q429 User’s Manual Chapter 6 Clock Generation Circuit P22MD P21MD - * P22C1 P21C1 - * P22C0 P21C0 - * P22D P21D - * ** 0 P20MD * 0 ...
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... P20(Port2 output-only port, does not have an register to select the data direction(i.e. input or output). P2MOD register (Address: 0F214H P2CON1 register (Address: 0F213H P2CON0 register (Address: 0F212H P2D register (Address: 0F210H – 17 ML610Q428/ML610Q429 User’s Manual Chapter 6 Clock Generation Circuit P22MD P21MD - * * P22C1 P21C1 - * * P22C0 P21C0 - * * P22D P21D - * * 0 P20MD 1 0 ...
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Time Base Counter Chapter 7 ...
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... Low-speed time base counter frequency adjust register LTBADJH : Low-speed time base counter frequency adjust register Figure 7-1 Configuration of Low-Speed Time Base Counter (LTBC) 7-bit Counter LTBR 8-bit Counter – 1 ML610Q428/ML610Q429 User’s Manual Chapter 7 Time Base Counter T32KHZ T16KHZ T8KHZ T4KHZ T2KHZ T1KHZ T512HZ T256HZ T128HZ ...
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... HTBDR: High-speed time base counter frequency divide register Figure 7-2 Configuration of High-Speed Time Base Counter Note: The frequency of HSCLK changes according to specified data in SYSC1 bit and SYSC0 bit of Frequency control register 0 (FON0) ML610Q428/ML610Q429 User’s Manual Chapter 7 Time Base Counter HTBDR HTBCLK 1/n-Counter 4 ...
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... High-speed time base counter 0F00BH frequency divide register Low-speed time base counter 0F00CH frequency adjustment register L Low-speed time base counter 0F00DH frequency adjustment register H ML610Q428/ML610Q429 User’s Manual Chapter 7 Time Base Counter Symbol (Byte) Symbol (Word) ⎯ LTBR ⎯ HTBDR LTBADJL ...
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... A TBC interrupt (128Hz interrupt, 64Hz interrupt, 32Hz interrupt, 16Hz interrupt, 8Hz interrupt, 4Hz interrupt, 2Hz interrupt, or 1Hz interrupt) may occur depending on the LTBR write timing (see Figure 7-4, “Interrupt Timing and Reset Timing by Writing to LTBR”). Therefore, take care in software programming. ML610Q428/ML610Q429 User’s Manual 5 4 ...
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... ML610Q428/ML610Q429 User’s Manual Chapter 7 Time Base Counter HTD2 HTD1 HTD0 R/W R/W R Description Frequency of HTBCLK (*1) 256 kHz 273 kHz 293 kHz 315 kHz ...
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... The LADJS and LADJ9 to LADJ0 bits are used to adjust frequency. Approx. −488ppm to +488ppm. Adjustment range: Adjustment accuracy: Approx. 0.48ppm See Section 7.3.3, “Low-Speed Time Base Counter Frequency Adjustment Function” for the correspondence between the frequency adjustment values (LTBADJH, LTBADJL) and adjustment ratio. ML610Q428/ML610Q429 User’s Manual LADJ5 LADJ4 LADJ3 ...
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... T16HZ T8HZ T4HZ T2HZ T1HZ Figure 7-4 Interrupt Timing and Reset Timing by Writing to LTBR ; EA←LTBR address [EA] ; 1st read [EA] ; 2nd read R1 ; Comparison for LTBR ; To MARK when the values do not coincide 7 – 7 ML610Q428/ML610Q429 User’s Manual Chapter 7 Time Base Counter Indicates interrupt timing ...
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... Figure 7-5 shows the output waveform of HTBCLK. High-speed clock HSCLK 1/n counter output HTBCLK High-speed time base counter Divide register HTBDR × 1/1 × 1/2 0FH 0EH Figure 7-5 Output Waveform of HTBCLK 7 – 8 ML610Q428/ML610Q429 User’s Manual Chapter 7 Time Base Counter × 1/3 0DH ...
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... ML610Q428/ML610Q429 User’s Manual Chapter 7 Time Base Counter Hexadecimal Frequency adjustment ratio (ppm) 3FFH +487.80 3FEH +487. 003H +1.43 002H +0.95 001H +0.48 000H 0 −0.48 7FFH −0.95 7FEH : : −487.80 401H −488.28 400H ...
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Timer (1kHzTM) Chapter 8 ...
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... L T1KCRH : 1 kHz timer count register H 1 kHz signal Binary/ternary T1KCRL counter Decimal×1 digit R R Figure 8-1 Configuration of 1 kHz Timer ８ – 1 ML610Q428/ML610Q429 User’s Manual Chapter 8 1 kHz Timer (1kHzTM) T1KINT Interrupt control T1KCRH Decimal×2 digits R ...
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... List of Registers Address Name 0F080H 1 kHz timer count register L 0F081H 1 kHz timer count register H 0F082H 1 kHz timer control register ML610Q428/ML610Q429 User’s Manual Chapter 8 1 kHz Timer (1kHzTM) Symbol (Byte) Symbol (Word) T1KCRL T1KCR T1KCRH ⎯ T1KCON ８ – 2 R/W ...
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... T1KCRL and T1KCRH are special function registers (SFRs) to read the decimal count values of the 1 kHz timer. When the write operation to T1KCRL or T1KCRH, the valid bit of T1KCRL or T1KCRH is "0" respectively. [Description of Bits] • T1KC11 to T1KC0 (T1KCRH: bits T1KCRL: bits T1KC11 to T1KC0 indicate the count values of the 1 kHz timer. ML610Q428/ML610Q429 User’s Manual ⎯ ...
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... Stops 1 kHz timer operation (initial value). 1 Starts 1 kHz operation. • T1KSEL (bit 1) The T1LSEL bit is used to select the interrupt period of the 1 kHz timer. The interrupt can be selected. T1KSEL interrupt (initial value interrupt ML610Q428/ML610Q429 User’s Manual ⎯ ⎯ ⎯ R/W R/W R/W ...
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... MARK: L ER0, [EA] L ER2, [EA] ; CMP ER0, ER1 BNE MARK ; : Figure 8-2 Example of Program for Reading T1KCRL and T1KCRH ML610Q428/ML610Q429 User’s Manual ; First read ; Second read ; Comparison of T1KCRL and T1CKRH ; To MARK when not matched. ８ – 5 Chapter 8 1 kHz Timer (1kHzTM) ...
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Chapter 9 Timers ...
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... In 8-bit Timer Mode (Timers TMnCON0 TnCK R TMnCON1 TMnC 8 (b) 16-bit Timer Mode (Timers Timer control register 0 Timer control register 1 Timer data registers Timer counter registers Figure 9-1 Configuration of Timers 9 – 1 ML610Q428/ML610Q429 User’s Manual Chapter 9 Timers TMnINT Match Comparator 8 TMnD TMmINT Match Comparator 16 8 ...
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... Timer 0 control register 0 0F032H Timer 0 control register 1 0F033H 0F034H Timer 1 data register 0F035H Timer 1 counter register 0F036H Timer 1 control register 0 Timer 1 control register 1 0F037H ML610Q428/ML610Q429 User’s Manual Symbol (Byte) Symbol (Word) TM0D TM0DC TM0C TM0CON0 TM0CON TM0CON1 TM1D TM1DC TM1C ...
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... TM0D is a special function register (SFR) to set the value to be compared with the timer 0 counter register (TM0C) value. Note: Set TM0D when the timer stops. When “00H” is written in TM0D, TM0D is set to “01H”. ML610Q428/ML610Q429 User’s Manual T0D5 T0D4 T0D3 ...
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... TM1D is a special function register (SFR) to set the value to be compared with the value of the timer 1 counter register (TM1C). Note: Set TM1D when the timer stops. When “00H” is written in TM1D, TM1D is set to “01H”. ML610Q428/ML610Q429 User’s Manual T1D5 T1D4 ...
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... Timer clock System clock T0CK SYSCLK LSCLK 1/1～1/256LSCLK LSCLK HSCLK HTBCLK 1/1～1/256LSCLK HTBCLK HSCLK 1/1～1/256LSCLK External clock HSCLK ML610Q428/ML610Q429 User’s Manual T0C5 T0C4 T0C3 R/W R/W R TM0C read enable/disable Read enabled Read enabled. However, to prevent the reading of undefined data during incremental counting, read consecutively TM0C twice until the last data coincides the previous data ...
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... Timer clock System clock T1CK SYSCLK LSCLK 1/1～1/256LSCLK LSCLK HSCLK HTBCLK 1/1～1/256LSCLK HTBCLK HSCLK 1/1～1/256LSCLK External clock HSCLK ML610Q428/ML610Q429 User’s Manual T1C5 T1C4 T1C3 R/W R/W R TM1C read enable/disable Read enabled Read enabled. However, to prevent the reading of undefined ...
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... Prohibited (timer 0 does not operate) 1 Prohibited (timer 0 does not operate) 0 Prohibited (timer 0 does not operate) 1 Prohibited (timer 0 does not operate) 0 Prohibited (timer 0 does not operate) 1 External clock (P44/T02P0CK) Description 9 – 7 ML610Q428/ML610Q429 User’s Manual Chapter 9 Timers T0CS2 T0CS1 R/W R Description 0 T0CS0 ...
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... In 16-bit timer mode, timer 1 is incremented by a timer 0 overflow signal. A timer 0 interrupt (TM0INT) is not generated. T01M16 8-bit timer mode (initial value) 0 16-bit timer mode 1 ML610Q428/ML610Q429 User’s Manual Description 9 – 8 Chapter 9 Timers ...
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... Prohibited (timer 0 does not operate) 1 Prohibited (timer 0 does not operate) 0 Prohibited (timer 0 does not operate) 1 Prohibited (timer 0 does not operate) 0 Prohibited (timer 0 does not operate) 1 External clock (P44/T02P0CK) Description 9 – 9 ML610Q428/ML610Q429 User’s Manual Chapter 9 Timers T1CS2 T1CS1 R/W R Description 0 T1CS0 ...
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... The T0RUN bit is used for controlling count stop/start of timer 0. T0RUN 0 Stops counting. Starts counting. 1 • T0STAT (bit 7) The T0STAT bit is used for indicating “counting stopped”/”counting in progress” of timer 0. T0STAT Counting stopped. 0 Counting in progress. 1 ML610Q428/ML610Q429 User’s Manual ⎯ ⎯ ⎯ R/W R/W R ...
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... T1STAT (bit 7) The T1STAT bit is used for indicating “counting stopped”/”counting in progress” of timer 1. In 16-bit timer mode, this bit will read “0”. T1STAT Counting stopped Counting in progress. ML610Q428/ML610Q429 User’s Manual ⎯ ⎯ ⎯ R/W R/W R/W ...
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... Even if “0” is written to the TnRUN bits, counting operation continues up to the falling edge (the timer status flag (TnSTA “1” state) of the next timer clock pulse. Therefore, the timer interrupt (TMnINT) may occur TMI 9 – 12 ML610Q428/ML610Q429 User’s Manual Chapter 9 Timers ...
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... TMnD TMnINT ( Figure 9-3 One-Shot Timer Mode Operation Timing Diagram of Timer Note: In one-shot timer mode, When the count value of TM0C to TM1C and the timer data register (TMnD) coincide, TnRUN bits are cleared automatically . TMI 9 – 13 ML610Q428/ML610Q429 User’s Manual Chapter 9 Timers ...
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Chapter 10 PWM ...
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... PWMn duty register L PWMn duty register H PWMn duty buffer PWMn counter register L PWMn counter register H PWMn control register 0 PWMn control register 1 Figure 10-1 Configuration of PWMn Circuit 10 – 1 ML610Q428/ML610Q429 User’s Manual Chapter 10 PWM PnNEG PWnINT Output control circuit Duty Period match ...
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... PW0CON0 PW0CON1 PW1PL PW1PH PW1DL PW1DH PW1CL PW1CH PW1CON0 PW1CON1 PW2PL PW2PH PW2DL PW2DH PW2CL PW2CH PW2CON0 PW2CON1 10 – 2 ML610Q428/ML610Q429 User’s Manual Chapter 10 PWM Symbol (Word) R/W Size R/W 8/16 PW0P R/W 8 R/W 8/16 PW0D R/W 8 R/W 8/16 PW0C R/W ...
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... R/W R/W R/W At reset 1 1 PW0PH and PW0PL are special function registers (SFRs) to set the PWM0 periods. Note: When PW0PH or PW0PL is set to “0000H”, the PWM0 period buffer (PW0PBUF) is set to “0001H”. ML610Q428/ML610Q429 User’s Manual P0P5 P0P4 P0P3 R/W R/W ...
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... R/W R/W R/W At reset 1 1 PW1PH and PW1PL are special function registers (SFRs) to set the PWM1 periods. Note: When PW1PH or PW1PL is set to “0000H”, the PWM1 period buffer (PW1PBUF) is set to “0001H”. ML610Q428/ML610Q429 User’s Manual P1P5 P1P4 P1P3 R/W R/W ...
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... R/W R/W R/W At reset 1 1 PW2PH and PW2PL are special function registers (SFRs) to set the PWM2 periods. Note: When PW2PH or PW2PL is set to “0000H”, the PWM2 period buffer (PW2PBUF) is set to “0001H”. ML610Q428/ML610Q429 User’s Manual P2P5 P2P4 P2P3 R/W R/W ...
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... Access: R/W Access size: 8 bits Initial value: 00H PW0DH and PW0DL are special function registers (SFRs) to set the duties of PWM0. Note: Set PW0DH and PW0DL to values smaller than those to which PW0PH and PW0PL are set. ML610Q428/ML610Q429 User’s Manual P0D5 P0D4 ...
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... Access: R/W Access size: 8 bits Initial value: 00H PW1DH and PW1DL are special function registers (SFRs) to set the duties of PWM1. Note: Set PW1DH and PW1DL to values smaller than those to which PW1PH and PW1PL are set. ML610Q428/ML610Q429 User’s Manual P1D5 P1D4 ...
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... Access: R/W Access size: 8 bits Initial value: 00H PW2DH and PW2DL are special function registers (SFRs) to set the duties of PWM2. Note: Set PW2DH and PW2DL to values smaller than those to which PW2PH and PW2PL are set. ML610Q428/ML610Q429 User’s Manual P2D5 P2D4 ...
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... Read enabled. However, to prevent the reading of undefined data during counting, read consecutively PW0CH or PW0CL twice HSCLK until the last data coincides the previous data. LSCLK Read disabled Read enabled HSCLK LSCLK Read disabled HSCLK 10 – 9 ML610Q428/ML610Q429 User’s Manual Chapter 10 PWM P0C2 P0C1 R/W R/W R ...
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... Read enabled. However, to prevent the reading of undefined data during counting, read consecutively PW1CH or PW1CL twice HSCLK until the last data coincides the previous data. LSCLK Read disabled Read enabled HSCLK LSCLK Read disabled HSCLK 10 – 10 ML610Q428/ML610Q429 User’s Manual Chapter 10 PWM P1C2 P1C1 R/W R/W R ...
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... Read enabled. However, to prevent the reading of undefined data during counting, read consecutively PW2CH or PW2CL twice HSCLK until the last data coincides the previous data. LSCLK Read disabled Read enabled HSCLK LSCLK Read disabled HSCLK 10 – 11 ML610Q428/ML610Q429 User’s Manual Chapter 10 PWM P2C2 P2C1 R/W R/W R ...
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... The P0NEG bit is used to select the output logic. When the positive logic is selected, the initial value of PWM0 output is “1”, and when the negative logic is selected, the initial value of PWM0 output is “0”. P0NEG Positive logic (initial value) 0 Negative logic 1 ML610Q428/ML610Q429 User’s Manual ⎯ P0NEG P0IS1 ...
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... The P1NEG bit is used to select the output logic. When the positive logic is selected, the initial value of PWM1 output is “1”, and when the negative logic is selected, the initial value of PWM1 output is “0”. P1NEG Positive logic (initial value) 0 Negative logic 1 ML610Q428/ML610Q429 User’s Manual ⎯ P1NEG P1IS1 ...
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... The P2NEG bit is used to select the output logic. When the positive logic is selected, the initial value of PWM2 output is “1”, and when the negative logic is selected, the initial value of PWM2 output is “0”. P2NEG Positive logic (initial value) 0 Negative logic 1 ML610Q428/ML610Q429 User’s Manual ⎯ P2NEG P2IS1 ...
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... PWM0 output flag = “0” PWM0 output flag = “1” (initial value) 1 • P0STAT (bit 7) The P0STAT bit indicates “counting stopped or “counting in progress” of PWM0. P0STAT Counting stopped. (Initial value) 0 Counting in progress. 1 ML610Q428/ML610Q429 User’s Manual ⎯ ⎯ ⎯ R/W R/W R/W ...
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... PWM1 output flag = “0” PWM1 output flag = “1” (initial value) 1 • P1STAT (bit 7) The P1STAT bit indicates “counting stopped or “counting in progress” of PWM1. P1STAT Counting stopped. (Initial value) 0 Counting in progress. 1 ML610Q428/ML610Q429 User’s Manual ⎯ ⎯ ⎯ R/W R/W R/W ...
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... PWM2 output flag = “0” PWM2 output flag = “1” (initial value) 1 • P2STAT (bit 7) The P2STAT bit indicates “counting stopped or “counting in progress” of PWM2. P2STAT Counting stopped. (Initial value) 0 Counting in progress. 1 ML610Q428/ML610Q429 User’s Manual ⎯ ⎯ ⎯ R/W R/W R/W ...
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... PWPn PnCK (Hz) PWnD + PWPn PnCK (Hz) PWnP: PWMn period registers (PWnPH, PWnPL) setting value (0001H to 0FFFFH) PWnD: PWMn duty registers (PWnDH, PWnDL) setting value (0000H to 0FFFEH) Clock frequency selected by the PWMn control register 0 (PWnCON0) PnCK: ML610Q428/ML610Q429 User’s Manual ( – 18 Chapter 10 PWM ...
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... PWMn clock pulse. Therefore, the PWMn interrupt (PWnINT) may occur. 0000 0001 0002 7FFF 8000 8001 8000 7777 8000 A000 BBBB A000 T PWD T 2004 10 – 19 ML610Q428/ML610Q429 User’s Manual Chapter 10 PWM 8002 A000 A000 0000 0001 7777 7777 8000 8000 7777 BBBB BBBB A000 A000 BBBB PWP ...
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... P45C1 P44C1 * * * P4CON0 register (Address: 0F222H P45C0 P44C0 * * * P4DIR register (Address: 0F221H P45DIR P44DIR * * * P4D register (Address: 0F220H P46D P45D P44D * * * 10 – 20 ML610Q428/ML610Q429 User’s Manual Chapter 10 PWM P43MD1 P42MD1 P41MD1 P43MD0 P42MD0 P41MD0 P43C1 P42C1 P41C1 P43C0 P42C0 P41C0 1 ...
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... P3CON1 register (Address: 0F21BH P35C1 P34C1 - * 1 P3CON0 register (Address: 0F21AH P35C0 P34C0 - * 1 P3DIR register (Address: 0F219H P35DIR P34DIR - * 0 P3D register (Address: 0F218H P35D P34D - * ** 10 – 21 ML610Q428/ML610Q429 User’s Manual Chapter 10 PWM P32MD1 P31MD1 * * * P32MD0 P31MD0 * * * P33C1 P32C1 P31C1 * * * P33C0 P32C0 P31C0 * * * P33DIR P32DIR ...
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... P45C1 P44C1 * * * P4CON0 register (Address: 0F222H P45C0 P44C0 * * * P4DIR register (Address: 0F221H P45DIR P44DIR * * * P4D register (Address: 0F220H P46D P45D P44D * * * 10 – 22 ML610Q428/ML610Q429 User’s Manual Chapter 10 PWM P43MD1 P42MD1 P41MD1 * * * P43MD0 P42MD0 P41MD0 * * * P43C1 P42C1 P41C1 * * * P43C0 P42C0 P41C0 * ...
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... P3CON1 register (Address: 0F21BH P35C1 P34C1 - 1 * P3CON0 register (Address: 0F21AH P35C0 P34C0 - 1 * P3DIR register (Address: 0F219H P35DIR P34DIR - 0 * P3D register (Address: 0F218H P35D P34D - ** * 10 – 23 ML610Q428/ML610Q429 User’s Manual Chapter 10 PWM P32MD1 P31MD1 * * * P32MD0 P31MD0 * * * P33C1 P32C1 P31C1 * * * P33C0 P32C0 P31C0 * * * P33DIR P32DIR ...
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... Don’t care the data. P2MOD1 register (Address: 0F215H P2MOD0 register (Address: 0F214H P2CON1 register (Address: 0F213H P2CON0 register (Address: 0F212H P2D register (Address: 0F210H – 24 ML610Q428/ML610Q429 User’s Manual Chapter 10 PWM P22MD1 P21MD1 P20MD1 - * * P22MD0 P21MD0 P20MD0 - * * P22C1 P21C1 * * - P22C0 P21C0 * * - P22D P21D - * * ...
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... P3CON1 register (Address: 0F21BH P35C1 P34C1 - * * P3CON0 register (Address: 0F21AH P35C0 P34C0 - * * P3DIR register (Address: 0F219H P35DIR P34DIR - * * P3D register (Address: 0F218H P35D P34D - * * 10 – 25 ML610Q428/ML610Q429 User’s Manual Chapter 10 PWM P32MD1 P31MD1 * * * P32MD0 P31MD0 * * * P33C1 P32C1 P31C1 * * * P33C0 P32C0 P31C0 * * * P33DIR P32DIR ...
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Chapter 11 Watchdog Timer ...
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... WDT counter Reset interrupt control R WDT overflow “5AH” “0A5H” detection QN : Watchdog timer control register : Watchdog timer mode register 11 – 1 ML610Q428/ML610Q429 User’s Manual Chapter 11 Watchdog Timer WDT reset WDTINT Non-maskable interrupt RESET_S System reset WDP WDTCON Write Data bus ...
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... Description of Registers 11.2.1 List of Registers Address Name 0F00EH Watchdog timer control register 0F00FH Watchdog timer mode register ML610Q428/ML610Q429 User’s Manual Chapter 11 Watchdog Timer Symbol (Byte) Symbol (Word) ⎯ WDTCON ⎯ WDTMOD 11 – 2 R/W Size Initial value R/W 8 00H R/W ...
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... Untill the low-speed clock oscillation start, the WDP will not be inverted even if writing to the WDTCON. Therefore, please check the WDP before writing to the WDTCON to determine writing “5AH” or “0A5H”. Program example if ( WDP == 1 ){ WDTCON = 0xa5; } WDTCON = 0x5a; WDTCON = 0xa5; ML610Q428/ML610Q429 User’s Manual R/W R/W ...
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... These bits are used to select an overflow period of the watchdog timer. The WDT1 and WDT0 bits set a overflow period (TWOV) of the WDT counter. One of 125ms, 500ms, 2s, and 8s can be selected. WDT1 WDT0 0 0 125 500 (initial value ML610Q428/ML610Q429 User’s Manual ⎯ ⎯ ⎯ R/W R/W R Description 11 – 4 Chapter 11 Watchdog Timer 2 ...
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... Clear the WDT counter within the clear period of the WDT counter shown in Table 11-1. WDT1 WDT0 Table 11-1 Clear Period of WDT Counter T WOV 0 125 ms 1 500 ms 0 2000 ms 1 8000 ms 11 – 5 ML610Q428/ML610Q429 User’s Manual Chapter 11 Watchdog Timer ), a watchdog timer interrupt WOV T WCL Approx. 121 ms Approx. 496 ms Approx. 1996 ms Approx. 7996 ms ...
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... WDT counter is cleared. Occurrence of abnormality 2WDTMOD setting WOV Overflow period 11 – 6 ML610Q428/ML610Q429 User’s Manual Chapter 11 Watchdog Timer Program start WDTMOD Overflow 8Occurrence of 9Occurrence of WDTINT WDT reset T WOV Overflow period setting 5A A5 ...
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Synchronous Serial Port Chapter 12 ...
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... SIO0MOD1 SIO0BUFH, SIO0BUFL Serial port transmit/receive buffer L Serial port transmit/receive buffer H Serial port control register Serial port mode register 0 Serial port mode register 1 12 – 1 ML610Q428/ML610Q429 User’s Manual Chapter 12 Synchronous Serial Port SIO0INT P41/SCK0 P45/SCK0 P42/SOUT0 P46/SOUT0 Receive register SIO0RCH, L ...
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... Used for the tertiary function of the P40 and P44 pins. Synchronous clock input/output. Used for the tertiary function of the P41 and P45 pins. Transmit data output. Used for the tertiary function of the P42 and P46 pins. 12 – 2 ML610Q428/ML610Q429 User’s Manual Chapter 12 Synchronous Serial Port ...
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... L Serial port 0 transmit/receive 0F281H buffer H Serial port 0 control register 0F282H Serial port 0 mode register 0 0F284H 0F285H Serial port 0 mode register 1 ML610Q428/ML610Q429 User’s Manual Chapter 12 Synchronous Serial Port Symbol (Byte) Symbol (Word) SIO0BUFL SIO0BUF SIO0BUFH ⎯ SIO0CON SIO0MOD0 SIO0MOD SIO0MOD1 12 – ...
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... When data is written in SIO0BUFL and SIO0BUFH, the data is written in the transmit registers (SIO0TRL and SIO0TRH) and when data is read from SIO0BUFL and SIO0BUFH, the contents of the receive registers (SIO0RCL and SIO0RCH) are read. ML610Q428/ML610Q429 User’s Manual S0B5 ...
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... The S0EN bit is used to specify start of synchronous serial communication. Writing a “1” to this bit starts 8-/16-bit data communication. This bit is set to “0” automatically when 8-/16-bit data communication is terminated. The S0EN bit is set to “0” system reset. S0EN Stops communication. (Initial value) 0 Starts communication 1 ML610Q428/ML610Q429 User’s Manual ⎯ ⎯ ⎯ R/W ...
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... Note: • Do not change any of the SIO0MOD0 register settings during transmission/reception. • When the synchronous serial port is used, the tertiary functions of GPIO must be set. For the tertiary functions of Port 4, see Chapter 20, “Port 4”. ML610Q428/ML610Q429 User’s Manual ⎯ ⎯ ...
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... The S0CKT bit is used to select a tansfer clock output phase. S0CKT Clock type 0: Clock is output with a “H” level being the default. (Initial value) 0 Clock type 1: Clock is output with a “L” level being the default. 1 ML610Q428/ML610Q429 User’s Manual ⎯ S0CKT S0CK3 ...
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... Figure 12-2 Transmit Operation Waveforms of Synchronous Serial Port for Clock Type 0 (8-bit Length, LSB first) S0EN SCK0 SIO0TRL SOUT0 SIO0INT Figure 12-3 Transmit Operation Waveforms of Synchronous Serial Port for Clock Type 1 (8-bit Length, LSB first) ML610Q428/ML610Q429 User’s Manual Transmit data Transmit data 0 ...
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... SIO0INT Figure 12-5 Receive Operation Waveforms of Synchronous Serial Port for Clock Type 1 (8-bit Length, MSB first) Note: When the SOUT0 pin is set to the tertiary function output in receive mode, a “H” level is output from the SOUT0 output pin. ML610Q428/ML610Q429 User’s Manual ...
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... Figure 12-6 shows the transmit/receive operation waveforms of the synchronous serial port (16-bit length, LSB first, clock types 0). S0EN SCK0 SIO0TRH,L SOUT0 SIN0 Shift register SIO0RCH, L SIO0INT Figure 12-6 Transmit/Receive Operation Waveforms of Synchronous Serial Port (16-bit Length, LSB first, Clock Type 0) Transmit data – 10 ML610Q428/ML610Q429 User’s Manual Chapter 12 Synchronous Serial Port Receive data ...
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... P4CON0 register (Address: 0F222H P46C0 P45C0 P44C0 * * * P4DIR register (Address: 0F221H P46DIR P45DIR P44DIR * * * P4D register (Address: 0F220H P46D P45D P44D * * * 12 – 11 ML610Q428/ML610Q429 User’s Manual Chapter 12 Synchronous Serial Port P43MD1 P42MD1 P41MD1 * P43MD0 P42MD0 P41MD0 * P43C1 P42C1 P41C1 * P43C0 ...
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... P4CON0 register (Address: 0F222H P46C0 P45C0 P44C0 * * * P4DIR register (Address: 0F221H P46DIR P45DIR P44DIR * * * P4D register (Address: 0F220H P46D P45D P44D * * * 12 – 12 ML610Q428/ML610Q429 User’s Manual Chapter 12 Synchronous Serial Port P43MD1 P42MD1 P41MD1 * P43MD0 P42MD0 P41MD0 * P43C1 P42C1 P41C1 * P43C0 ...
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... P45C1 P44C1 P4CON0 register (Address: 0F222H P45C0 P44C0 P4DIR register (Address: 0F221H P45DIR P44DIR P4D register (Address: 0F220H P46D P45D P44D ** ** ** 12 – 13 ML610Q428/ML610Q429 User’s Manual Chapter 12 Synchronous Serial Port P43MD1 P42MD1 P41MD1 * * * P43MD0 P42MD0 P41MD0 * * * P43C1 P42C1 P41C1 * * * P43C0 P42C0 ...
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... P4CON0 register (Address: 0F222H P46C0 P45C0 P44C0 P4DIR register (Address: 0F221H P46DIR P45DIR P44DIR P4D register (Address: 0F220H P46D P45D P44D ** ** ** 12 – 14 ML610Q428/ML610Q429 User’s Manual Chapter 12 Synchronous Serial Port P43MD1 P42MD1 P41MD1 * * * P43MD0 P42MD0 P41MD0 * * * P43C1 P42C1 P41C1 * * * P43C0 ...
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... Figure 12-7 Waves of timer0 int clock (1/1), timer1 int clock (1/1), timer0 int clock (1/2) and timer1 int clock (1/2). 12 – 15 ML610Q428/ML610Q429 User’s Manual Chapter 12 Synchronous Serial Port ...
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Chapter 13 UART ...
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... Used for the secondary function of the P02 pin. UART0 data input pin I Used for the secondary function of the P42 pin. UART0 data output pin Used for the secondary function of the P43 pin. 13 – 1 ML610Q428/ML610Q429 User’s Manual Chapter 13 UART P43/TXD0 UA0INT UA0STAT Description ...
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... UART0 control register 0F292H UART0 mode register 0 0F293H UART0 mode register 1 0F294H UART0 baud rate register L 0F295H UART0 baud rate register H 0F296H UART0 status register ML610Q428/ML610Q429 User’s Manual Symbol (Byte) Symbol (Word) ⎯ UA0BUF ⎯ UA0CON UA0MOD0 UA0MOD UA0MOD1 UA0BRTL UA0BRT UA0BRTH ⎯ ...
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... The bits not required when 5-bit, 6-bit, 7-bit, or 8-bit data length is slected become invalid in transmit mode and are set to “0” in receive mode. Note: For operation in transmit mode, be sure to set the transmit mode (UA0MOD0 and UA0MOD1) before setting transmit data in UAOBUF. ML610Q428/ML610Q429 User’s Manual U0B5 ...
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... The U0EN bit is used to specify the UART communication operation start. When U0EN is set to “1”, UART communication starts. In transmit mode, this bit is automatically set to “0” at termination of transmission. In receive mode, receive operation is continued. To terminate reception, set the bit to “0” by software. U0EN 0 Stops communication. (Initial value) 1 Starts communication. ML610Q428/ML610Q429 User’s Manual ⎯ ⎯ ⎯ R/W ...
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... When selecting the P42 pin as the receive data input pin necessary to configure settings for the Port 4 secondary functions. For the details of the Port 4 secondary function settings, see Chapter 20, “Port 4”. ML610Q428/ML610Q429 User’s Manual — ...
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... The U0STP bit is used to select the stop bit length in the communication of the UART. U0STP 0 1 stop bit (initial value stop bits • U0NEG (bit 5) The U0NEG bit is used to select positive logic or negative logic in the communication of the UART. U0NEG 0 Positive logic (initial value) 1 Negative logic ML610Q428/ML610Q429 User’s Manual U0NEG U0STP U0PT1 R/W R/W R ...
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... The U0DIR bit is used to select LSB first or MSB first in the communication of the UART. U0DIR 0 LSB first (initial value) 1 MSB first Note: Always set the UA0MOD1 register while communication is stopped, and do not rewrite it during communication. ML610Q428/ML610Q429 User’s Manual Description 13 – 7 Chapter 13 UART ...
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... For the relationship between the count value of the baud rate generator and baud rate, see Section 15.3.2, “Baud Rate”. Note: Always set the UA0BRTL and UA0BRTH registers while communication is stopped, and do not rewrite them during communication. ML610Q428/ML610Q429 User’s Manual ...
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... When the parity of the received data and the parity bit attached to the data do not coincide, this bit is set to “1”. U0PER is updated whenever data is received. The U0PER bit is fixed to “0” in transmit mode. U0PER 0 No parity error (initial value) 1 Parity error ML610Q428/ML610Q429 User’s Manual — — U0FUL R/W ...
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... UA0BUF after checking that the U0FUL flag has been set to “0”. The U0FUL bit is fixed to “0” in receive mode. U0FUL 0 There is no data in the transmit/receive buffer. (Initial value) 1 There is data in the transmit/receive buffer. ML610Q428/ML610Q429 User’s Manual Description 13 – 10 Chapter 13 UART ...
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... Data bit • Data bit length……….. bits variable • Parity bit………...........With or without parity bit selectable • Stop bit………............. stop bits selectable 13 – 11 ML610Q428/ML610Q429 User’s Manual Chapter 13 UART Parity Stop Stop ...
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... ML610Q428/ML610Q429 User’s Manual Chapter 13 UART Period of 1 bit UA0BRTH Approx. 824 μs 00H Approx. 412 μs 00H Approx. 208 μs 03H Approx. 104 μs 01H Approx. 52 μs 00H Approx. 26 μs 00H Approx. 17.3 μs 00H Approx. 8.8 μ ...
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... U0B7 is “0” at completion of reception. U0B5 U0B4 U0B3 U0B7 and U0B6 are “0” at completion of reception. U0B4 U0B3 U0B7, U0B6, and U0B5 are “0” at completion of reception. 13 – 13 ML610Q428/ML610Q429 User’s Manual Chapter 13 UART LSB reception U0B2 U0B0 U0B1 MSB reception LSB reception U0B2 ...
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... U0EN bit is reset to “0” and a UART0 interrupt is requested. The valid period for the next transmit data to be written to the transmit/receive buffer is from the generation of an interrupt to the termination of stop bit transmission. (6) ML610Q428/ML610Q429 User’s Manual 13 – 14 Chapter 13 UART ...
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... Figure 13-5 Operation Timing in Transmission 13 – 15 ML610Q428/ML610Q429 User’s Manual Chapter 13 UART ...
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... Reception continues until the U0EN bit is reset to “0” by the program. When the U0EN bit is reset to “0” during reception, the data received may be destroyed. When the U0EN bit is reset to “0” during the “U0EN reset enable period” in Figure 13.6, the data received is protected. ML610Q428/ML610Q429 User’s Manual 13 – 16 Chapter 13 UART ...
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... Figure 13-6 Operation Timing in Reception 13 – 17 ML610Q428/ML610Q429 User’s Manual Chapter 13 UART ...