MMA8450QT Freescale Semiconductor, MMA8450QT Datasheet - Page 44

• Manufacturer Part Number: MMA8450QT
• Description: Board Mount Accelerometers 12bit 3-Axis FIFO HPF PL
• Manufacturer: Freescale Semiconductor

Specifications of MMA8450QT

• Sensing Axis: X, Y, Z
• Acceleration: 2 g, 4 g, 8 g
• Digital Output - Number Of Bits: 12 bit
• Supply Voltage (max): 1.89 V
• Supply Voltage (min): 1.71 V
• Supply Current: 3 uA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Shutdown: Yes
• Sensitivity: 0.976 mg/digit, 1.953 mg/digit, 3.906 mg/digit
• Package / Case: QFN-16
• Output Type: Digital
• Package Type: QFN
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Product Depth (mm): 3mm
• Product Height (mm): 1mm
• Product Length (mm): 3mm
• Mounting: Surface Mount
• Pin Count: 16
• Acceleration Range: ± 2g, ± 4g, ± 8g
• No. Of Axes: 3
• Ic Interface Type: I2C, Serial
• Sensor Case Style: QFN
• No. Of Pins: 16
• Supply Voltage Range: 1.71V To 1.89V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Appendix A
Table 64. MMA8450Q Register Map
44
MMA8450Q
Reg
0C
0D
1C
1D
00
01
02
03
04
05
06
07
08
09
0A
0B
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1E
1F
20
21
22
23
24
25
26
27
28
HP_FILTER_CUTOFF
PL_P_L_THS_REG1
PL_P_L_THS_REG2
PL_P_L_THS_REG3
PL_L_P_THS_REG1
PL_L_P_THS_REG2
PL_L_P_THS_REG3
FF_MT_COUNT_1
PL_PRE_STATUS
XYZ_DATA_CFG
PL_BF_ZCOMP
OUT_X_DELTA
OUT_Y_DELTA
OUT_Z_DELTA
FF_MT_CFG_1
FF_MT_SRC_1
FF_MT_CFG_2
FF_MT_SRC_2
FF_MT_THS_1
INT_SOURCE
OUT_X_MSB
OUT_Y_MSB
OUT_Z_MSB
OUT_X_MSB
OUT_Y_MSB
OUT_Z_MSB
OUT_X_LSB
OUT_Y_LSB
OUT_Z_LSB
PL_STATUS
WHO_AM_I
PL_COUNT
F_STATUS
F_12DATA
F_SETUP
F_8DATA
SYSMOD
STATUS
STATUS
STATUS
PL_CFG
Name
FF/Motion Threshold 1 R/W
FF/Motion Debounce 1 R/W
Threshold Setting21 R/W
FF/Motion Config. 2 R/W
8-bit Transient X Data R
8-bit Transient Y Data R
Threshold Setting 1 R/W
Threshold Setting 2 R/W
Threshold Setting 3 R/W
Threshold Setting 1 R/W
Threshold Setting 3 R/W
8-bit Transient Z Data R
FF/Motion Source 1 R
FF/Motion Source 2 R
HP Filter Setting R/W
Previous PL Status R
PL Configuration R/W
Portrait-to-Landscape
Portrait-to-Landscape
Portrait-to-Landscape
Landscape-to-Portrait
Landscape-to-Portrait
Landscape-to-Portrait
PL Back/Front and Z
Compensation R/W
12-bit FIFO Data R
PL Debounce R/W
8-bit FIFO Data R
Interrupt Status R
Data Config. R/W
FF/Motion Config.
FIFO Setup R/W
System Mode R
12-bit X Data R
12-bit X Data R
12-bit Y Data R
12-bit Y Data R
12-bit Z Data R
12-bit Z Data R
FIFO Status R
Data Status R
8-bit X Data R
8-bit Y Data R
8-bit Z Data R
Data Status R
Data Status R
ID Register R
PL Status R
Definition
1 R/W
P_L_THS[7]
P_L_THS[7]
P_L_THS[7]
L_P_THS[7]
L_P_THS[7]
L_P_THS[7]
SRC_ASLP
F_MODE1
DBNCE[7]
DBCNTM
DBCNTM
BKFR[1]
ZYXOW
ZYXOW
ZYXOW
NEWLP
F_OVF
PERR
XD11
YD11
ZD11
XD11
YD11
ZD11
XD11
Bit 7
XD7
YD7
ZD7
FDE
ELE
ELE
D7
—
—
—
0
0
0
0
0
-
F_WMRK_FLAG
P_L_THS[6]
P_L_THS[6]
P_L_THS[6]
L_P_THS[6]
L_P_THS[6]
L_P_THS[6]
SRC_FIFO
F_MODE0
DBNCE[6]
BKFR[0]
FGERR
PL_EN
XD10
YD10
ZD10
XD10
YD10
ZD10
XD10
THS6
Bit 6
ZOW
ZOW
ZOW
XD6
YD6
ZD6
OAE
OAE
LO
LO
EA
D6
EA
—
0
0
0
0
0
0
SRC_TRANS
P_L_THS[5]
P_L_THS[5]
P_L_THS[5]
L_P_THS[5]
L_P_THS[5]
L_P_THS[5]
F_WMRK5
DBNCE[5]
F_CNT5
ZHEFE
ZHEFE
THS5
YOW
YOW
YOW
Bit 5
ZHE
ZHE
XD9
YD9
ZD9
XD9
YD9
ZD9
XD5
YD5
ZD5
XD9
D5
—
0
0
0
0
0
0
0
-
-
-
-
SRC_LNDPRT
P_L_THS[4]
P_L_THS[4]
P_L_THS[4]
L_P_THS[4]
L_P_THS[4]
L_P_THS[4]
F_WMRK4
DBNCE[4]
F_CNT4
LAPO[2]
LAPO[2]
ZLEFE
ZLEFE
THS4
XOW
XOW
XOW
Bit 4
XD4
YD4
XD8
YD8
ZD8
XD8
YD8
ZD8
ZD4
XD8
ZLE
ZLE
D4
—
0
0
0
0
0
0
0
-
-
SRC_PULSE
P_L_THS[3]
P_L_THS[3]
P_L_THS[3]
L_P_THS[3]
L_P_THS[3]
L_P_THS[3]
F_WMRK3
DBNCE[3]
F_CNT3
LAPO[1]
LAPO[1]
ZYXDR
ZYXDR
ZYXDR
YHEFE
YHEFE
THS3
Bit 3
YHE
YHE
XD7
YD7
ZD7
XD3
XD7
YD3
YD7
ZD3
ZD7
XD3
YD3
ZD3
XD7
XD3
D3
—
—
0
0
-
-
SRC_FF_MT_1
P_L_THS[2]
P_L_THS[2]
P_L_THS[2]
L_P_THS[2]
L_P_THS[2]
L_P_THS[2]
F_WMRK2
DBNCE [2]
ZLOCK[2]
F_CNT2
LAPO[0]
LAPO[0]
GOFF[2]
ZDEFE
YLEFE
YLEFE
THS2
Bit 2
ZDR
ZDR
ZDR
XD6
YD6
ZD6
XD2
XD6
YD2
YD6
ZD2
ZD6
XD2
YD2
ZD2
XD6
XD2
YLE
YLE
D2
—
0
0
Freescale Semiconductor
SRC_FF_MT_2
P_L_THS[1]
P_L_THS[1]
P_L_THS[1]
L_P_THS[1]
L_P_THS[1]
L_P_THS[1]
F_WMRK1
SYSMOD1
DBNCE [1]
BAFRO[1]
BAFRO[1]
ZLOCK[1]
F_CNT1
GOFF[1]
YDEFE
XHEFE
XHEFE
THS1
SEL1
Bit 1
YDR
YDR
YDR
XHE
XHE
XD5
YD5
ZD5
XD1
XD5
YD1
YD5
ZD1
ZD5
XD1
YD1
ZD1
XD5
XD1
D1
—
SRC_DRDY
P_L_THS[0]
P_L_THS[0]
P_L_THS[0]
L_P_THS[0]
L_P_THS[0]
L_P_THS[0]
F_WMRK0
SYSMOD0
DBNCE [0]
BAFRO[0]
BAFRO[0]
ZLOCK[0]
Sensors
F_CNT0
GOFF[0]
XDEFE
XLEFE
XLEFE
THS0
SEL0
Bit 0
XDR
XDR
XD0
YD0
XDR
XD0
YD0
XD0
XD4
YD4
ZD4
XD4
YD4
ZD0
ZD4
ZD0
XD4
XLE
XLE
D0
—