MMA8450QT Freescale Semiconductor, MMA8450QT Datasheet - Page 23

• Manufacturer Part Number: MMA8450QT
• Description: Board Mount Accelerometers 12bit 3-Axis FIFO HPF PL
• Manufacturer: Freescale Semiconductor

Specifications of MMA8450QT

• Sensing Axis: X, Y, Z
• Acceleration: 2 g, 4 g, 8 g
• Digital Output - Number Of Bits: 12 bit
• Supply Voltage (max): 1.89 V
• Supply Voltage (min): 1.71 V
• Supply Current: 3 uA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Shutdown: Yes
• Sensitivity: 0.976 mg/digit, 1.953 mg/digit, 3.906 mg/digit
• Package / Case: QFN-16
• Output Type: Digital
• Package Type: QFN
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Product Depth (mm): 3mm
• Product Height (mm): 1mm
• Product Length (mm): 3mm
• Mounting: Surface Mount
• Pin Count: 16
• Acceleration Range: ± 2g, ± 4g, ± 8g
• No. Of Axes: 3
• Ic Interface Type: I2C, Serial
• Sensor Case Style: QFN
• No. Of Pins: 16
• Supply Voltage Range: 1.71V To 1.89V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

YDR is set whenever a new acceleration sample related to the Y-axis is available. YDR is cleared anytime OUT_Y_MSB register
is read. In order to enable the monitoring and assertion of this bit, the YDR bit requires the Y-axis event detection flag to be
enabled (bit YDEFE = 1 inside XYZ_DATA_CFG register).
XDR is set to 1 whenever a new acceleration sample related to the X-axis is available. XDR is cleared anytime OUT_X_MSB
register is read. In order to enable the monitoring and assertion of this bit, the XDR bit requires the X-axis to event detection flag
to be enabled (bit XDEFE = 1 inside XYZ_DATA_CFG register).
The ZDR and ZOW flag generation requires the Z-axis event flag generator to be enabled (ZDEFE = 1) in the XYZ_DATA_CFG
register.
The YDR and YOW flag generation requires the Y-axis event flag generator to be enabled (YDEFE = 1) in the XYZ_DATA_CFG
register.
The XDR and XOW flag generation requires the X-axis event flag generator to be enabled (XDEFE = 1) in the XYZ_DATA_CFG
register.
The ZYXDR and ZYXOW flag generation is requires the Z-axis, Y-axis, X-axis event flag generator to be enabled (ZDEFE = 1,
YDEFE = 1, XDEFE = 1) in the XYZ_DATA_CFG register.
0x01, 0x02, 0x03: OUT_MSB 8-Bit XYZ Data Registers
OUT_X_MSB, OUT_Y_MSB, OUT_Z_MSB so applications needing only 8-bit results can use these registers and can ignore the
OUT_X_LSB, OUT_Y_LSB, OUT_Z_LSB. The status Register 0x00, OUT_X_MSB, OUT_Y_MSB, OUT_Z_MSB are duplicated
in the auto-incrementing address range of 0x00 to 0x03 to reduce reading the status followed by 8-bit axis data to a 4 byte
sequence.
0x05 - 0x0A: OUT_MSB and OUT_LSB 12-Bit XYZ Data Registers
(0x06), OUT_Y_LSB (0x07), OUT_Y_MSB (0x08), OUT_Z_LSB(0x09), OUT_Z_MSB (0x0A) are stored in auto-incrementing
address range of 0x04 to 0x0A to reduce reading the status followed by 12-bit axis data to 7 bytes.
0x01 OUT_X_MSB: X_MSB Register (Read Only)
0x08 OUT_Y_MSB: Y_MSB Register (Read Only)
0x09 OUT_Z_LSB: Z_LSB Register (Read Only)
Sensors
Freescale Semiconductor
0x02 OUT_Y_MSB: Y_MSB Register (Read Only)
0x06 OUT_X_MSB: X_MSB Register (Read Only)
0x07 OUT_Y_LSB: Y_LSB Register (Read Only)
0x0A OUT_Z_MSB: Z_MSB Register (Read Only)
0x05 OUT_X_LSB: X_LSB Register (Read Only)
0x03 OUT_Z_MSB: Z_MSB Register (Read Only)
X, Y and Z-axis data is expressed as 2’s complement numbers. The most significant 8-bits are stored together in
X, Y and Z-axis data is expressed as 2’s complement numbers. The STATUS (0x04), OUT_X_LSB (0x05), OUT_X_MSB
XD11
YD11
XD11
YD11
Bit 7
Bit 7
ZD11
Bit 7
ZD11
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
0
0
0
Bit 6
XD10
YD10
XD10
YD10
ZD10
Bit 6
Bit 6
ZD10
Bit 6
Bit 6
Bit 6
Bit 6
Bit 6
Bit 6
0
0
0
Bit 5
Bit 5
Bit 5
Bit 5
Bit 5
Bit 5
Bit 5
Bit 5
Bit 5
XD9
YD9
XD9
YD9
ZD9
ZD9
0
0
0
Bit 4
Bit 4
Bit 4
Bit 4
Bit 4
Bit 4
Bit 4
Bit 4
Bit 4
XD8
YD8
XD8
YD8
0
ZD8
ZD8
0
0
Bit 3
ZD3
Bit 3
Bit 3
Bit 3
Bit 3
Bit 3
Bit 3
Bit 3
Bit 3
XD7
YD7
ZD7
XD3
XD7
YD3
YD7
ZD7
Bit 2
ZD2
Bit 2
Bit 2
Bit 2
Bit 2
Bit 2
Bit 2
Bit 2
Bit 2
YD6
ZD6
XD2
XD6
YD2
YD6
XD6
ZD6
Bit 1
ZD1
Bit 1
Bit 1
Bit 1
Bit 1
Bit 1
Bit 1
Bit 1
Bit 1
ZD5
XD1
YD1
ZD5
XD5
YD5
XD5
YD5
MMA8450Q
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
ZD4
XD0
YD0
Bit 0
YD4
XD4
YD4
ZD0
ZD4
XD4
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