MMA8450QT Freescale Semiconductor, MMA8450QT Datasheet - Page 11

• Manufacturer Part Number: MMA8450QT
• Description: Board Mount Accelerometers 12bit 3-Axis FIFO HPF PL
• Manufacturer: Freescale Semiconductor

Specifications of MMA8450QT

• Sensing Axis: X, Y, Z
• Acceleration: 2 g, 4 g, 8 g
• Digital Output - Number Of Bits: 12 bit
• Supply Voltage (max): 1.89 V
• Supply Voltage (min): 1.71 V
• Supply Current: 3 uA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Shutdown: Yes
• Sensitivity: 0.976 mg/digit, 1.953 mg/digit, 3.906 mg/digit
• Package / Case: QFN-16
• Output Type: Digital
• Package Type: QFN
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Product Depth (mm): 3mm
• Product Height (mm): 1mm
• Product Length (mm): 3mm
• Mounting: Surface Mount
• Pin Count: 16
• Acceleration Range: ± 2g, ± 4g, ± 8g
• No. Of Axes: 3
• Ic Interface Type: I2C, Serial
• Sensor Case Style: QFN
• No. Of Pins: 16
• Supply Voltage Range: 1.71V To 1.89V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 4. I
1. All values referred to VIH (min) and VIL (max) levels.
2. t
3. A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the VIH (min) of the SCL signal) to bridge the
4. The maximum t
5. t
6. t
7. A Fast-mode I
8. Cb = total capacitance of one bus line in pF.
9. The maximum t
10.In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used, designers should allow for
2.3
Sensors
Freescale Semiconductor
SCL Clock Frequency
Bus Free Time between STOP and START Condition
Repeated START Hold Time
Repeated START Setup Time
STOP Condition Setup Time
SDA Data Hold Time
SDA Valid Time
SDA Valid Acknowledge Time
SDA Setup Time
SCL Clock Low Time
SCL Clock High Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Pulse width of spikes on SDA and SCL that must be suppressed by input filter
Pull-up = 1 k
Pull-up = 1 k
undefined region of the falling edge of SCL.
by a transition time. This maximum must only be met if the device does not stretch the LOW period (t
stretches the SCL, the data must be valid by the set-up time before it releases the clock.
automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the
SCL signal, it must output the next data bit to the SDA line t
specification) before the SCL line is released. Also the acknowledge timing must meet this set-up time
This allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA/SCL bus lines without exceeding
the maximum specified t
this when considering bus timing
HD;DAT
VD;DAT
VD;ACK
= time for data signal from SCL LOW to SDA output (HIGH or LOW, depending on which one is worse).
2
is the data hold time that is measured from the falling edge of SCL, applies to data in transmission and the acknowledge.
= time for Acknowledgement signal from SCL LOW to SDA output (HIGH or LOW, depending on which one is worse).
C Slave Timing Values
I
2
Ω
Ω
C Interface Characteristic
2
Cb = 400 pF
Cb = 20 pF
(5)
HD;DAT
C device can be used in a Standard-mode I
f
for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage t
(2)
could be 3.45 μs and 0.9 μs for Standard-mode and Fast-mode, but must be less than the maximum of t
(3) (8) (9) (10)
f
.
(6)
Parameter
(1)
2
r
C system, but the requirement t
(max) + t
SU;DAT
= 1000 + 250 = 1250 ns (according to the Standard-mode I
Symbol
t
t
t
t
t
t
t
HD;STA
SU;STA
SU;STO
HD;DAT
VD;DAT
VD;ACK
SU;DAT
t
t
t
f
HIGH
LOW
SCL
BUF
t
SP
t
t
r
f
SU;DAT
250 ns must then be met. This will
100
50
Min
1.3
0.6
0.6
0.6
4.7
LOW
I
2
0
0
4
C Standard Mode
(3)
(7)
) of the SCL signal. If the clock
0.9
0.9
1000
Max
TBD
f
400
300
50
is specified at 250 ns.
(4)
(4)
(4)
VD;DAT
MMA8450Q
or t
Unit
kHz
kHz
Ns
Ns
Ns
Ns
μs
μs
μs
μs
μs
μs
μs
μs
μs
VD;ACK
2
C
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