MMA8450QT Freescale Semiconductor, MMA8450QT Datasheet - Page 29

• Manufacturer Part Number: MMA8450QT
• Description: Board Mount Accelerometers 12bit 3-Axis FIFO HPF PL
• Manufacturer: Freescale Semiconductor

Specifications of MMA8450QT

• Sensing Axis: X, Y, Z
• Acceleration: 2 g, 4 g, 8 g
• Digital Output - Number Of Bits: 12 bit
• Supply Voltage (max): 1.89 V
• Supply Voltage (min): 1.71 V
• Supply Current: 3 uA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Shutdown: Yes
• Sensitivity: 0.976 mg/digit, 1.953 mg/digit, 3.906 mg/digit
• Package / Case: QFN-16
• Output Type: Digital
• Package Type: QFN
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Product Depth (mm): 3mm
• Product Height (mm): 1mm
• Product Length (mm): 3mm
• Mounting: Surface Mount
• Pin Count: 16
• Acceleration Range: ± 2g, ± 4g, ± 8g
• No. Of Axes: 3
• Ic Interface Type: I2C, Serial
• Sensor Case Style: QFN
• No. Of Pins: 16
• Supply Voltage Range: 1.71V To 1.89V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 20. PL_STATUS Register Description
1. The default power up state is BAFRO (Undefined), LAPO (Undefined), and no Lockout for orientation function.
NEWLP is set to 1 whenever a change in LO, BAFRO, or LAPO occurs. NEWLP bit is cleared anytime PL_STATUS register is
read.
0x19: PL_PRE_STATUS Portrait/Landscape Previous Data Status Register
has been described in Register 0x18.
0x1A: PL_CFG Portrait/Landscape Configuration Register
threshold offset.
0x1B: PL_COUNT Portrait Landscape Debounce Register
the data rate set by the selected system ODR and PL_COUNT registers. Any change to the ODR or device mode transitioning
from ACTIVE to STANDBY or vice versa resets the internal landscape/portrait internal debounce counters.
the relationship between the ODR, the step per count and the duration.
Sensors
Freescale Semiconductor
Table 21. PL_CFG Register Description
0x19 PL_PRE_STATUS Register (Read Only)
0x1A PL_CFG Register (Read/Write)
0x1B PL_COUNT Register (Read/Write)
This register provides the previous orientation data from the previous reading. These register definitions are the same as what
This register configures the behavior of the debounce counters and also sets the Landscape/Portrait 1g lockout mechanism
This register sets the debounce counter for the orientation state transition. The minimum debounce latency is determined by
The debounce counter scales with the ODR, like many of the debounce counters in the other functional blocks.
DBNCE[7]
DBCNTM
DBCNTM
LAPO[2:0]
BAFRO[1:0]
PL_EN
GOFF
Bit 7
Bit 7
NEWLP
Bit 7
—
LO
(1)
Debounce counter mode selection. Default value: 1.
0: Decrements debounce whenever condition of interest is no longer valid.
1: Clears counter whenever condition of interest is no longer valid.
Portrait-Landscape Detection Enable. Default value: 0.
0: Portrait-Landscape Detection is Disabled.
1: Portrait-Landscape Detection is Enabled.
1g lockout threshold offset expressed in steps of 50 mg. Default value: 011 = 1.15g.
The offset specified by the GOFF is added or subtracted from 1g to achieve the optimal 1g lockout threshold.
If GOFF = 011, then the resulting 1g lockout threshold is
000: No offset.
DBNCE[6]
Landscape-Portrait status change flag. Default value: 0.
0: No change, 1: BAFRO and/or LAPO and/or Z-tilt lockout value has changed
Z-Tilt Angle Lockout. Default value: 0.
0: Lockout condition has not been detected.
1: Z-Tilt lockout trip angle has been exceeded. Lockout has been detected.
Back or Front orientation. Default value: 00.
00: Undefined. This is the default power up state.
01: Front: Device is in the front facing orientation.
10: Back: Device is in the back facing orientation.
Landscape/Portrait orientation. Default value: 000.
000: Undefined. This is the default power up state.
001: Portrait Up
010: Portrait Down
011: Landscape Right
100: Landscape Left
Bit 6
Bit 6
LO
PL_EN
Bit 6
DBNCE[5]
Bit 5
Bit 5
-—
Bit 5
—
DBNCE[4]
Bit 4
LAPO[2]
Bit 4
Bit 4
—
DBNCE[3]
Bit 3
±
LAPO[1]
(1g + 150 mg).
Bit 3
Bit 3
—
DBNCE [2]
Bit 2
LAPO[0]
Bit 2
GOFF[2]
Bit 2
DBNCE [1]
BAFRO[1]
Bit 1
Bit 1
GOFF[1]
Bit 1
Table 22
DBNCE [0]
BAFRO[0]
MMA8450Q
GOFF[0]
Bit 0
Bit 0
Bit 0
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