MMA8450QT Freescale Semiconductor, MMA8450QT Datasheet - Page 40

• Manufacturer Part Number: MMA8450QT
• Description: Board Mount Accelerometers 12bit 3-Axis FIFO HPF PL
• Manufacturer: Freescale Semiconductor

Specifications of MMA8450QT

• Sensing Axis: X, Y, Z
• Acceleration: 2 g, 4 g, 8 g
• Digital Output - Number Of Bits: 12 bit
• Supply Voltage (max): 1.89 V
• Supply Voltage (min): 1.71 V
• Supply Current: 3 uA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Shutdown: Yes
• Sensitivity: 0.976 mg/digit, 1.953 mg/digit, 3.906 mg/digit
• Package / Case: QFN-16
• Output Type: Digital
• Package Type: QFN
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Product Depth (mm): 3mm
• Product Height (mm): 1mm
• Product Length (mm): 3mm
• Mounting: Surface Mount
• Pin Count: 16
• Acceleration Range: ± 2g, ± 4g, ± 8g
• No. Of Axes: 3
• Ic Interface Type: I2C, Serial
• Sensor Case Style: QFN
• No. Of Pins: 16
• Supply Voltage Range: 1.71V To 1.89V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

value depend on the ODR chosen (see
Table 52. ASLP_COUNT Relationship with ODR
functions will still function in sleep mode at the sleep ODR. Only the functions that have been selected for “Wake From Sleep”
will wake the device.
Motion/FF1 and Motion/FF2 and the FIFO. One or more of these functions can be enabled. In order to wake the device, functions
are provided namely, Transient, Orientation, Tap, and the two Motion/Freefall. Note that the FIFO does not wake the device. The
Auto-Wake/Sleep interrupt does not affect the wake/sleep, nor does the data ready interrupt. The FIFO gate (bit 7) in Register
0x3A, when set, will hold the last data in the FIFO before transitioning to a different ODR. After the buffer is flushed, it will accept
new sample data at the current ODR. See Register 0x3A for the wake from sleep bits.
FS1 bits in Register 0x38 Ctrl Reg1. If Auto-Sleep interrupt is enabled, transitioning from Active mode to Auto-Sleep mode and
vice versa generates an interrupt.
0x38: CTRL_REG1 System Control 1 Register
Table 54. Sleep Mode Poll Rate Description
functional blocks are overwritten by the data rate set by the ASLP_RATE field in Register 0x38.
Table 53. CTRL_REG1 Description
40
0x38 CTRL_REG1 Register (Read/Write)
Table 55. System Output Data Rate Selection
MMA8450Q
ASLP_RATE1
D7-D0 defines the minimum duration time to change current ODR value from DR to ASLP_RATE. Time step and maximum
In order to wake the device, the desired function or functions must be enabled and set to “Wake From Sleep”. All enabled
MMA8450Q has 6 functions that can be used to keep the sensor from falling asleep namely, Transient, Orientation, Tap,
If the Auto-Sleep bit is disabled, then the device can only toggle between Standby and Wake Mode by writing to the FS0 and
It is important to note that when the device is in Auto-Sleep mode, the system ODR and the data rate for all the system
DR[2:0] bits select the output data rate (ODR) for acceleration samples. The default value is 000 for a data rate of 400 Hz.
ASLP_RATE [1:0]
DR2
Bit 7
0
0
DR[2:0]
FS[1:0]
Output Data Rate (ODR)
ASLP_RATE1
ASLP_RATE0
DR1
0
0
1
1
0
0
Bit 6
12.5
1.56
400
200
100
50
This register configures the Auto-Wake sample frequency when the device is in Sleep Mode.
See
Data rate selection. Default value: 000
Full Scale selection. Default value: 00
(00: Standby mode; 01: active mode ±2g; 10: active mode ±4g; 11: active mode ±8g)
Table 54
DR0
0
1
Bit 5
for more information.
0
Table
52).
Output Data Rate (ODR)
Bit 4
DR2
ASLP_RATE0
400 Hz
200 Hz
0
1
0
1
Bit 3
DR1
Duration
0 to 162s
0 to 81s
0 to 81s
0 to 81s
0 to 81s
0 to 81s
Bit 2
DR0
Time Between Data Samples
Frequency (Hz)
Bit 1
2.5 ms
FS1
Freescale Semiconductor
5 ms
12.5
1.56
50
25
320 ms
320 ms
320 ms
320 ms
320 ms
640 ms
Step
Bit 0
FS0
Sensors