MMA8450QT Freescale Semiconductor, MMA8450QT Datasheet - Page 39

• Manufacturer Part Number: MMA8450QT
• Description: Board Mount Accelerometers 12bit 3-Axis FIFO HPF PL
• Manufacturer: Freescale Semiconductor

Specifications of MMA8450QT

• Sensing Axis: X, Y, Z
• Acceleration: 2 g, 4 g, 8 g
• Digital Output - Number Of Bits: 12 bit
• Supply Voltage (max): 1.89 V
• Supply Voltage (min): 1.71 V
• Supply Current: 3 uA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Shutdown: Yes
• Sensitivity: 0.976 mg/digit, 1.953 mg/digit, 3.906 mg/digit
• Package / Case: QFN-16
• Output Type: Digital
• Package Type: QFN
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Product Depth (mm): 3mm
• Product Height (mm): 1mm
• Product Length (mm): 3mm
• Mounting: Surface Mount
• Pin Count: 16
• Acceleration Range: ± 2g, ± 4g, ± 8g
• No. Of Axes: 3
• Ic Interface Type: I2C, Serial
• Sensor Case Style: QFN
• No. Of Pins: 16
• Supply Voltage Range: 1.71V To 1.89V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 50. Time Step for PULSE Detection Window at ODR and Power Mode
Table 51. ASLP_COUNT Description
0x35: PULSE_LTCY Pulse Latency Timer Register
are ignored. Note: This timer must be set for single pulse and for double pulse.
Mode multiplied by 255. Notice that the time step is twice the duration if the device is operating in Low Power mode, as shown
below.
0x36: PULSE_WIND Second Pulse Time Window Register
the start of the second pulse event must be detected provided the device has been configured for double pulse detection. The
detected second pulse width must be shorter than the time limit constraints specified by the PULSE_TMLT register, but the end
of the double pulse need not finish within the time specified by the PULSE_WIND register.
Mode multiplied by 255.
6.7
0x37: ASLP_COUNT Auto-Sleep Inactivity Timer Register
specified in the DR[2:0] to ASLP_RATE (Reg 0x38) value provided the SLPE bit is set to a logic ‘1’ in the CTRL_REG2 register.
Table 49. Time Step for PULSE Latency at ODR and Power Mode
0x36 PULSE_WIND Register (Read/Write)
Sensors
Freescale Semiconductor
0x37 ASLP_COUNT Register (Read/Write)
0x35 PULSE_LTCY Register (Read/Write)
The bits Ltcy7 through Ltcy0 define the time interval that starts after the first pulse detection. During this time interval, all pulses
The minimum time step for the pulse latency is defined in
The bits Wind7 through Wind0 define the maximum interval of time that can elapse after the end of the latency interval in which
The minimum time step for the pulse window is defined in
For additional information on how to configure the device for the Auto-Sleep/Wake feature, refer to AN3921.
The ASLP_COUNT register sets the minimum time period of inactivity required to change current ODR value from the value
D[7-0]
Wind7
Bit 7
Ltcy7
Bit 7
Bit 7
D7
Output Data Rate (Hz)
Auto-Sleep Registers
Output Data Rate (Hz)
Duration value. Default value: 0000 0000
12.5
1.56
12.5
1.56
400
200
100
400
200
100
Wind6
50
50
Bit 6
Ltcy6
Bit 6
Bit 6
D6
Wind5
Ltcy5
Bit 5
Bit 5
Bit 5
D5
Wind4
Ltcy4
Bit 4
Bit 4
Bit 4
Step at Normal Mode
Step at Normal Mode
D4
Table
Table
1.25 ms
1.25 ms
2.5 ms
5.0 ms
2.5 ms
5.0 ms
10 ms
10 ms
10 ms
10 ms
10 ms
10 ms
49. The maximum time is the time step at the ODR and Power
50. The maximum time is the time step at the ODR and Power
Wind3
Ltcy3
Bit 3
Bit 3
Bit 3
D3
Wind2
Ltcy2
Bit 2
Bit 2
Bit 2
D2
Step at Low Power Mode
Step at Low Power Mode
Wind1
Ltcy1
Bit 1
Bit 1
Bit 1
D1
2.5 ms
5.0 ms
20 ms
20 ms
20 ms
20 ms
2.5 ms
5.0 ms
20 ms
20 ms
20 ms
20 ms
MMA8450Q
Ltcy0
Wind0
Bit 0
Bit 0
Bit 0
D0
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