MMA8450QT Freescale Semiconductor, MMA8450QT Datasheet

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... Shock and vibration monitoring (mechatronic compensation, shipping and warranty usage logging) • User interface (menu scrolling by orientation change, tap detection for button replacement Part Number MMA8450QT MMA8450QR1 This document contains certain information on a new product. Specifications and information herein are subject to change without notice. ...

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... Serial I C Interface .................................................................................................................................................... 17 Table 8. Serial Interface Pin Description ................................................................................................................... 17 2 5.10 Operation ................................................................................................................................................. 18 2 Table Address Selection Table ....................................................................................................................... 18 Single Byte Read ......................................................................................................................................................... 18 Multiple Byte Read ....................................................................................................................................................... 18 Single Byte Write ......................................................................................................................................................... 18 Multiple Byte Write ....................................................................................................................................................... 19 2 Table 10 device Address Sequence .................................................................................................................. 19 2 Figure 11 Timing Diagram ................................................................................................................................. 19 MMA8450Q 2 Sensors Freescale Semiconductor ...

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... PL_PRE_STATUS Register (Read Only) ...................................................................................................29 0x1A: PL_CFG Portrait/Landscape Configuration Register .........................................................................................29 0x1A PL_CFG Register (Read/Write) ..................................................................................................................29 Table 20. PL_CFG Register Description ...................................................................................................................29 0x1B: PL_COUNT Portrait Landscape Debounce Register .........................................................................................29 0x1B PL_COUNT Register (Read/Write) ............................................................................................................29 Table 21. PL_STATUS Register Description ............................................................................................................29 Table 22. PL_COUNT Relationship with the ODR ....................................................................................................30 Sensors Freescale Semiconductor MMA8450Q 3 ...

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... Table 41. TRANSIENT_COUNT relationship with the ODR ..................................................................................... 36 Table 42. TRANSIENT_SRC Description ................................................................................................................. 36 6.6 Tap Detection Registers .......................................................................................................................................... 37 0x2F: PULSE_CFG Pulse Configuration Register ....................................................................................................... 37 0x2F PULSE_CFG Register (Read/Write) ........................................................................................................... 37 Table 43. PULSE_CFG Description .......................................................................................................................... 37 0x30: PULSE_SRC Pulse Source Register ................................................................................................................. 37 0x30 PULSE_SRC Register (Read Only) ........................................................................................................... 37 Table 44. TPULSE_SRC Description ....................................................................................................................... 37 MMA8450Q 4 Sensors Freescale Semiconductor ...

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... Figure 14. Distribution of Post Board Mounted Devices (1 count = 3.9 mg) ............................................................48 Figure 15. 2g/4g/8g X-axis TCS (%/°C) ....................................................................................................................49 Figure 16. 2g/4g/8g Y-axis TCS (%/°C) ....................................................................................................................50 Figure 17. 2g/4g/8g Z-axis TCS (%/°C) ....................................................................................................................51 Figure 18. 2g/4g/8g X-axis TCO (mg/°C) ..................................................................................................................52 Figure 19. 2g/4g/8g Y-axis TCO (mg/°C) ..................................................................................................................53 Figure 20. 2g/4g/8g Z-axis TCO (mg/°C) ..................................................................................................................54 Package Dimensions................................................................................................................................................................55 Sensors Freescale Semiconductor MMA8450Q 5 ...

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... Hysteresis jolt) and Z-lockout Active Mode Mode Auto-Wake Mode Auto-Sleep Figure 1. Block Diagram Embedded 2 DSP I C Functions Shake Detection Tap and through Double Tap Motion Detection Threshold SLEEP Mode (Reduced Sampling Rate (BOTTOM VIEW) Freescale Semiconductor SDA SCL Sensors ...

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... Top View Pin 1 LL Xout @ 0g Yout @ -1g Zout @ 0g Xout @ -1g Yout @ 0g Zout @ 0g Xout @ 0g Yout @ 1g Zout @ 0g 1.8V SCL 1.8V SDA 4.7kΩ 4.7kΩ Sensors Freescale Semiconductor PU Earth Gravity LR PD Xout @ 1g Yout @ 0g Zout @ 0g Figure 3. Landscape/Portrait Orientation 1. VDD 2 NC 0.1μ MMA8450Q ...

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... C Least Significant Bit of the Device Address 2 C Bus Enabled; 0: Shutdown Mode connections are open drain and therefore require a pull-up resistor as shown Pin Status Input Input Input Open Drain Input Open Drain Input Input Output Input Output Input Input Input Input Input Sensors Freescale Semiconductor ...

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... Before board mount. 2. See appendix for distribution graphs. 3. Post board mount offset specification are based layer PCB. 4. Self-test in one direction only. These are approximate values and can change by ±100 counts. Sensors Freescale Semiconductor Test Conditions Symbol FS[1:0] set to 01 FS[1:0] set to 10 ...

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... VIL I = 500 μA VOH 500 μA VOL 500 μA VOLS O ODR BW BT Ton (1) Min Typ Max Unit 1.71 1.8 1. μ 120 μA 72 132 225 <1 μA 3 μA 0.75*VDD V 0.3*VDD V 0.9*VDD V 0.1*VDD V 0.1*VDD V 0.9*ODR ODR 1.1*ODR Hz ODR/2 Hz 1.55 ms 3/ODR s Sensors Freescale Semiconductor ...

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... This allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified 10.In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used, designers should allow for this when considering bus timing Sensors Freescale Semiconductor 2 I Symbol Min f SCL t 1 ...

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... This is an ESD sensitive, improper handling can cause permanent damage to the part. MMA8450Q 12 2 Figure Slave Timing Diagram Symbol g max VDD Vin D drop STG Symbol HBM MM CDM — Value Unit 10,000 g -0 -0.3 to VDD + 0.3 V 1.8 M -40 to +85 °C -40 to +125 °C Value Unit ±2000 V ±200 V ±500 V ±100 mA Sensors Freescale Semiconductor ...

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... Standby to Active. These are all noted in the device memory map register table. For more detail on how to use the Sleep and Wake modes and how to transition between these modes, please refer to the functionality section of this document. Sensors Freescale Semiconductor VDD = OFF STANDBY ...

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... For more information on how to configure the MMA8450Q in Low Power Mode and the power consumption benefits of Low Power Mode and Auto-Wake/Sleep with specific application examples, refer to Freescale application note, AN3921. MMA8450Q bus. The FIFO can also provide Sensors Freescale Semiconductor ...

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... CTRL_REG5 Register (0x3C). Registers 0x2B – 0x2E are the dedicated Transient Detection configuration registers. For details on the benefits of the embedded Transient Detection function along with specific application examples and recommended configuration settings, please refer to Freescale application note, AN3918. Sensors Freescale Semiconductor MMA8450Q 15 ...

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... This is user configurable. The default angle is 32° but it can be set as low as 25°. Figure 9. Illustration of Z-Tilt Angle Lockout Transition MMA8450Q 16 PORTRAIT 90 0° Landscape Figure 8. Illustration of Portrait-to-Landscape Transition PORTRAIT ° 90 NORMAL DETECTION Z-LOCK = 32.142° REGION LOCKOUT REGION 0° Landscape ° Portrait-to-Landscape ° Trip Angle = 60 0° Landscape Freescale Semiconductor Sensors ...

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... External 4.7 kΩ pull-up resistors connected to VDD are expected for SDA and SCL. When the bus is free both the lines are high. The I (400 kHz), and normal mode (100 kHz) I Sensors Freescale Semiconductor Event Flag 0 Event Flag 1 FIFO ...

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... Master transmits a stop condition (SP) to the data transfer. The data sent to the MMA8450Q is now stored in the appropriate register. MMA8450Q 18 Slave Address (SA0 = 1) 0011101 Figure 11 shows the timing diagram for the accelerometer 8-bit I Table 9. Comment Factory Default 2 C Sensors Freescale Semiconductor ...

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... ST Device Address [6:0] W Master Slave < Multiple Byte Write > ST Device Address [6:0] W Master Slave Legend ST: Start Condition SP: Stop Condition SR: Repeated Start Condition AK: Acknowledge Sensors Freescale Semiconductor [0] [6:0] SA0 Device Address 0 0x1C 0 0x1C 1 0x1D 1 0x1D Register Address [7:0] SR Device Address [6: Register Address [7:0] ...

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... Cutoff frequency is set to 4Hz @ 400Hz Landscape/Portrait orientation status Landscape/Portrait previous orientation Landscape/Portrait configuration. 1g Lockout offset is set to default value of 1.15g. Debounce counters are clear during invalid sequence condition. Landscape/Portrait debounce counter ± Back-Front Trip threshold is 75°. Z-Lockout angle is 32.14° Sensors Freescale Semiconductor ...

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... Note: Auto-increment addresses which are not a simple increment are highlighted in bold. The auto-increment addressing is only enabled when 2 device registers are read using I C burst read mode. Therefore the internal storage of the auto-increment address is clear whenever a stop-bit is detected. Sensors Freescale Semiconductor 0x1D 0x1E 00011010 0x1E 0x1F ...

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... In order to enable the monitoring and assertion of this bit, the ZDR bit requires the Z-axis event detection flag to be enabled (bit ZDEFE = 1 inside XYZ_DATA_CFG register). MMA8450Q 22 Alias Status 0x00 = 0x04 = DR_STATUS (0x0B) 0x00 = 0x04 = F_STATUS (0x10) Bit 4 Bit 3 Bit 2 XOW ZYXDR ZDR Bit 1 Bit 0 YDR XDR Sensors Freescale Semiconductor ...

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... YD10 YD9 0x09 OUT_Z_LSB: Z_LSB Register (Read Only) Bit 7 Bit 6 Bit 0x0A OUT_Z_MSB: Z_MSB Register (Read Only) Bit 7 Bit 6 Bit 5 ZD11 ZD10 ZD9 Sensors Freescale Semiconductor Bit 4 Bit 3 XD8 XD7 Bit 4 Bit 3 YD8 YD7 Bit 4 Bit 3 ZD8 ZD7 Bit 4 Bit XD3 ...

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... Bit 3 F_CNT5 F_CNT4 F_CNT3 Event Description 2 C address 0x01. The F_12DATA Bit 2 Bit 1 Bit 0 XD2 XD1 XD0 Bit 2 Bit 1 Bit 0 YD2 YD1 YD0 Bit 2 Bit 1 Bit 0 ZD2 ZD1 ZD0 Bit 2 Bit 1 Bit Bit 2 Bit 1 Bit 0 F_CNT2 F_CNT1 F_CNT0 Sensors Freescale Semiconductor ...

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... Mode Bits. The watermark bits are configurable to set the number of samples of data to trigger the watermark event flag. The maximum number of samples is 32. For more information on the FIFO configuration refer to AN3920. 0x13 F_SETUP: FIFO Setup Register (Read/Write) Bit 7 Bit 6 Bit 5 F_MODE1 F_MODE0 F_WMRK5 Sensors Freescale Semiconductor Bit 4 Bit 3 XD8 XD7 Bit 4 Bit XD3 ...

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... If the FIFO buffer is not emptied before the arrival of the next sample, then the FGERR bit in register 0x14 is asserted. The FGERR remains asserted as long as the FIFO buffer remains un-emptied. Emptying the FIFO buffer clears the FGERR bit. MMA8450Q 26 Description Bit 4 Bit Bit 2 Bit 1 Bit 0 0 SYSMOD1 SYSMOD0 Sensors Freescale Semiconductor 2 C ...

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... Otherwise logic ‘0’ the X,Y,Z interrupt is not active. SRC_DRDY This bit is asserted when the ZYXOW and/or ZYXDR is set and the interrupt has been enabled. This bit is cleared by reading the STATUS and register. Sensors Freescale Semiconductor Bit 4 Bit 3 Bit 2 SRC_LNDPRT SRC_PULSE ...

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... Bit 4 Bit 3 — LAPO[2] LAPO[1] Bit 2 Bit 1 Bit 0 ZDEFE YDEFE XDEFE Bit 2 Bit 1 Bit 0 0 SEL1 SEL0 Fc (Hz (Hz) @ ODR = 12.5 Hz ODR = 1.563 Hz 0.125 0.01 0.063 0.007 0.031 0.004 0.016 0.002 Bit 2 Bit 1 Bit 0 LAPO[0] BAFRO[1] BAFRO[0] Freescale Semiconductor Sensors ...

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... Bit 5 DBNCE[7] DBNCE[6] DBNCE[5] The debounce counter scales with the ODR, like many of the debounce counters in the other functional blocks. the relationship between the ODR, the step per count and the duration. Sensors Freescale Semiconductor Bit 4 Bit 3 -— LAPO[2] LAPO[1] Bit 5 ...

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... Z > 105° and Z < 255° Z > 110° and Z < 250° Z > 115° and Z < 245° Table 28 Bit 2 Bit 1 Bit 0 P_L_THS[2] P_L_THS[1] P_L_THS[0] Bit 2 Bit 1 Bit 0 P_L_THS[2] P_L_THS[1] P_L_THS[0] Bit 2 Bit 1 Bit 0 P_L_THS[2] P_L_THS[1] P_L_THS[0] Sensors Freescale Semiconductor ...

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... Landscape-to-Portrait Threshold Register 2. Default value: 60° → 0100_0001. 0x22 PL_L_P_THS_REG3 Register (Read/Write) Bit 7 Bit 6 Bit 5 L_P_THS[7] L_P_THS[6] L_P_THS[5] Table 31. PL_L_P_THS_REG3 Description L_P_THS Landscape-to-Portrait Threshold Register 3. Default value: 60° → 1010_0010. Sensors Freescale Semiconductor PL_P_L_THS_REG2 0x17 0x75 0x18 0x14 0x18 0xF3 0x1A 0x32 0x1B 0x92 ...

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... Bit 4 Bit 3 ZLEFE YHEFE PL_L_P_THS_REG3 0x22 0xD4 0x92 0x77 0x92 0x33 0x00 0x00 0x31 0xD9 0x71 0xB9 0x41 0xA2 0x91 0x8F 0x31 0x81 0x71 0x77 Bit 2 Bit 1 YLEFE XHEFE Freescale Semiconductor Bit 0 XLEFE Sensors ...

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... Decrementing of the debounce counter acts as a median filter enabling the system to filter out irregular spurious events which might impede the detection of the event. Sensors Freescale Semiconductor Bit 4 Bit 3 Bit 2 ...

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... An ODR of 100 Hz and a FF_MT_COUNT_1 value of 15 would result in a debounce response time of 150 ms. MMA8450Q 34 Figure 12. DBCNTM Bit Function Bit 4 Bit Step 2 640 ms (a) DBCNTM = 1 (b) DBCNTM = 0 (c) Bit 2 Bit 1 Bit Duration Range 2.5 ms – 0.63s 5 ms – 1.275s 10 ms – 2.55s 20 ms – 5. – 20.4s 640 ms – 163s Sensors Freescale Semiconductor ...

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... The interrupt for the transient event is cleared by reading the status register. 0x2C TRANSIENT_SRC Register (Read Only) Bit 7 Bit 6 Bit 5 — — Sensors Freescale Semiconductor Bit 4 Bit 3 ZLEFE YHEFE Bit 4 Bit 3 ZLE YHE ...

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... An ODR of 100 Hz and a TRANSIENT_COUNT value of 15 would result in a debounce response time of 150 ms. MMA8450Q 36 Bit 4 Bit 3 THS4 THS3 Bit 4 Bit Step 2 640 ms Bit 2 Bit 1 Bit 0 THS2 THS1 THS0 Bit 2 Bit 1 Bit Duration Range 2.5 ms – 0.637s 5 ms – 1.275s 10 ms – 2.55s 20 ms – 5. – 20.4s 640 ms – 163s Sensors Freescale Semiconductor ...

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... Single Y event detected Double pulse on X-axis event. Default value: 0. XDPE 0: no event detected; 1: Double X event detected Single pulse on X-axis event. Default value: 0. XSPE 0: no event detected; 1: Single X event detected Sensors Freescale Semiconductor Bit 4 Bit 3 Bit 2 ZSPEFE YDPEFE YSPEFE Bit 4 ...

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... Maximum time for a given ODR is the minimum time step Step at Normal Mode 0.625 ms 1. Bit 2 Bit 1 Bit 0 THSX2 THSX1 THSX0 Bit 2 Bit 1 Bit 0 THSY2 THSY1 THSY0 Bit 2 Bit 1 Bit 0 THSZ2 THSZ1 THSZ0 Bit 2 Bit 1 Bit 0 Tmlt2 Tmlt1 Tmlt0 Step at Low Power Mode 1.25 ms 2 Sensors Freescale Semiconductor ...

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... ASLP_COUNT Register (Read/Write) Bit 7 Bit 6 Bit Table 51. ASLP_COUNT Description D[7-0] Duration value. Default value: 0000 0000 Sensors Freescale Semiconductor Bit 4 Bit 3 Ltcy4 Ltcy3 Table 49. The maximum time is the time step at the ODR and Power Step at Normal Mode 1.25 ms 2.5 ms 5.0 ms ...

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... Bit 4 Bit 3 0 DR2 DR1 for more information. ASLP_RATE0 Output Data Rate (ODR) 400 Hz 200 Hz Step 320 ms 320 ms 320 ms 320 ms 320 ms 640 ms Bit 2 Bit 1 Bit 0 DR0 FS1 FS0 Frequency (Hz 12.5 1.56 Time Between Data Samples 2 Sensors Freescale Semiconductor ...

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... Note: The I C communication system is reset to avoid accidental corrupted data access. 0x3A: CTRL_REG3 Interrupt Control Register 0x3A CTRL_REG3 Register (Read/Write) Bit 7 Bit 6 FIFO_GATE WAKE_TRANS WAKE_LNDPRT Sensors Freescale Semiconductor 100 12.5 Hz 1.563 Hz Mode Standby Active Active Active Bit 4 Bit 3 ...

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... Freefall/Motion1 interrupt disabled; 1: Freefall/Motion1 interrupt enabled Interrupt Enable. Default value: 0. INT_EN_FF_MT_2 0: Freefall/Motion2 interrupt disabled; 1: Freefall/Motion2 interrupt enabled Interrupt Enable. Default value: 0. INT_EN_DRDY 0: Data Ready interrupt disabled; 1: Data Ready interrupt enabled MMA8450Q 42 Bit 4 Bit 3 INT_EN_LNDPRT INT_EN_PULSE INT_EN_FF_MT_1 Description Bit 2 Bit 1 Bit 0 INT_EN_FF_MT_2 INT_EN_DRDY Sensors Freescale Semiconductor ...

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... OFF_Z Offset Correction Z Register 0x3F OFF_Z Register (Read/Write) Bit 7 Bit 6 Bit Table 63. OFF_Z Description D7-D0 Z-axis offset trim LSB value. Default value: 0000_0000. Sensors Freescale Semiconductor Bit 4 Bit 3 Description Figure 10 uses the corresponding bit field in the CTRL_REG5 register to determine Bit 4 Bit ...

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... L_P_THS[1] L_P_THS[0] YHEFE YLEFE XHEFE YHE YLE XHE THS3 THS2 THS1 YHEFE YLEFE XHEFE YHE YLE XHE Sensors Freescale Semiconductor Bit 0 XDR XD4 YD4 ZD4 XDR XD0 XD4 YD0 YD4 ZD0 ZD4 XDR XD0 YD0 ZD0 — XD4 XD0 XDEFE SEL0 ...

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... Control Reg4 R/W (Interrupt 3B CTRL_REG4 INT_EN_ASLP Enable Map) Control reg5 R/W 3C CTRL_REG5 INT_CFG_ASLP INT_CFG_FIFO INT_CFG_TRANS INT_CFG_LNDPRT (Interrupt Configuration) 3D OFF_X X 8-bit offset 3E OFF_Y Y 8-bit offset 3F OFF_Z Z 8-bit offset Sensors Freescale Semiconductor THS6 THS5 THS4 — — — — — — — — THS6 THS5 THS4 D7 ...

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... Range ±8g +7.996g +7.992g — +0.004g 0.000g -0.004g — -7.996g -8.000g Range ±8g +7.936g +7.872g — +0.064g 0.000g -0.064g — -7.936g -8.000g Sensors Freescale Semiconductor ...

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... Appendix B Figure 13. Distribution of Pre Board Mounted Devices Tested in Sockets (1 count = 3.9 mg) Sensors Freescale Semiconductor MMA8450Q 47 ...

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... Figure 14. Distribution of Post Board Mounted Devices (1 count = 3.9 mg) MMA8450Q 48 Sensors Freescale Semiconductor ...

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... Sensors Freescale Semiconductor Figure 15. 2g/4g/8g X-axis TCS (%/°C) MMA8450Q 49 ...

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... MMA8450Q 50 Figure 16. 2g/4g/8g Y-axis TCS (%/°C) Sensors Freescale Semiconductor ...

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... Sensors Freescale Semiconductor Figure 17. 2g/4g/8g Z-axis TCS (%/°C) MMA8450Q 51 ...

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... MMA8450Q 52 Figure 18. 2g/4g/8g X-axis TCO (mg/°C) Sensors Freescale Semiconductor ...

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... Sensors Freescale Semiconductor Figure 19. 2g/4g/8g Y-axis TCO (mg/°C) MMA8450Q 53 ...

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... MMA8450Q 54 Figure 20. 2g/4g/8g Z-axis TCO (mg/°C) Sensors Freescale Semiconductor ...

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... Sensors Freescale Semiconductor PACKAGE DIMENSIONS CASE 2077-01 ISSUE O 16-LEAD QFN MMA8450Q 55 ...

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... MMA8450Q 56 PACKAGE DIMENSIONS CASE 2077-01 ISSUE O 16-LEAD Q Sensors Freescale Semiconductor ...

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... Sensors Freescale Semiconductor PACKAGE DIMENSIONS CASE 2077-01 ISSUE O 16-LEAD Q MMA8450Q 57 ...

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... Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “ ...