WM8352GEB/V Wolfson Microelectronics, WM8352GEB/V Datasheet - Page 42
WM8352GEB/V
Manufacturer Part Number
WM8352GEB/V
Description
Audio CODECs Audio CODEC plus pwr management
Manufacturer
Wolfson Microelectronics
Datasheet
1.WM8352GEBV.pdf
(335 pages)
Specifications of WM8352GEB/V
Number Of Adc Inputs
2
Number Of Dac Outputs
2
Conversion Rate
48 KSPS
Interface Type
Serial (2-Wire, 3-Wire, 4-Wire)
Resolution
12 bit
Operating Supply Voltage
3.7 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
BGA
Minimum Operating Temperature
- 25 C
Number Of Channels
2 ADC/2 DAC
Supply Current
260 uA
Thd Plus Noise
- 83 dB
Audio Codec Type
Stereo
No. Of Adcs
2
No. Of Dacs
2
No. Of Input Channels
8
No. Of Output Channels
6
Adc / Dac Resolution
24bit
Adcs / Dacs Signal To Noise Ratio
95dB
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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WM8352
11.4 3-WIRE SERIAL CONTROL MODE
Figure 30 3-Wire Serial Control Interface
w
The 3-wire control interface uses the CSB, SCLK and SDATA pins, which are referenced to the
digital buffer supply, DBVDD. (In 3-wire mode, CSB is provided on GPIO7.)
3-wire control mode is selected by setting SPI_3WIRE = 1 and SPI_4WIRE = 0.
In 3-wire control mode, a control word consists of 24 bits. The first bit is the read/write bit (R/W),
which is followed by 7 address bits (A6 to A0) that determine which control register is accessed. The
remaining 16 bits (B15 to B0) are data bits, corresponding to the 16 bits in each control register.
In 3-wire mode, every rising edge of SCLK clocks in one data bit from the SDATA pin. A rising edge
on CSB latches in a complete control word consisting of the last 24 bits.
In Write operations (R/W=0), all SDATA bits are driven by the controlling device.
In Read operations (R/W=1), the SDATA pin is driven by the controlling device to clock in the register
address, after which the WM8352 drives the SDATA pin to output the applicable data bits.
Similarly to 2-wire control mode, the WM8352 transmits logic 1 by tri-stating the SDATA pin, rather
than pulling it high. An external pull-up resistor is required to pull the SDATA line high so that the
logic 1 can be recognised by the master.
The 3-wire control mode timing is illustrated in Figure 30.
PD, March 2010, Rev 4.2
Production Data
42
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