WM8352GEB/V Wolfson Microelectronics, WM8352GEB/V Datasheet - Page 261

• Manufacturer Part Number: WM8352GEB/V
• Description: Audio CODECs Audio CODEC plus pwr management
• Manufacturer: Wolfson Microelectronics

Specifications of WM8352GEB/V

• Number Of Adc Inputs: 2
• Number Of Dac Outputs: 2
• Conversion Rate: 48 KSPS
• Interface Type: Serial (2-Wire, 3-Wire, 4-Wire)
• Resolution: 12 bit
• Operating Supply Voltage: 3.7 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: BGA
• Minimum Operating Temperature: - 25 C
• Number Of Channels: 2 ADC/2 DAC
• Supply Current: 260 uA
• Thd Plus Noise: - 83 dB
• Audio Codec Type: Stereo
• No. Of Adcs: 2
• No. Of Dacs: 2
• No. Of Input Channels: 8
• No. Of Output Channels: 6
• Adc / Dac Resolution: 24bit
• Adcs / Dacs Signal To Noise Ratio: 95dB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Production Data
REGISTER
Register 6Fh BEEP Volume
Register 70h AI Formating
w
REGISTER
ADDRESS
AI Formating
ADDRESS
R111 (6Fh)
R112 (70h)
Volume
BEEP
BIT
11:10
BIT
7:5
15
9:8
15
13
12
IN3R_OUT2R_VOL[2:0]
AIF_LRCLK_INV
AIF_BCLK_INV
AIF_FMT[1:0]
IN3R_TO_OUT2R
AIF_WL[1:0]
LABEL
AIF_TRI
LABEL
DEFAULT
10
10
0
0
0
DEFAULT
000
0
0 = normal
1 = inverted
Sets Output enables for LRCLK and BCLK and
ADCDAT to inactive state
0 = normal
1 = forces pins to Hi-Z
LRCLK clock polarity
0 = normal
1 = inverted
DSP Mode – mode A/B select
0 = MSB is available on 2nd BCLK rising edge after
LRCLK rising edge (mode A)
1 = MSB is available on 1st BCLK rising edge after
LRCLK rising edge (mode B)
Data word length
11 = 32 bits
10 = 24 bits
01 = 20 bits
00 = 16 bits
Note: When using the Right-Justified data format
(FMT=00), the maximum word length is 24 bits.
00 = Right-justified
01 = Left justified
10 = I2S
11 = DSP / PCM mode
Beep mixer enable
0 = disabled
1 = enabled
Beep mixer volume:
000 = -15dB
… in +3dB steps
111 = +6dB
DESCRIPTION
DESCRIPTION
PD, March 2010, Rev 4.2
REFER TO
REFER TO
WM8352
261