WM8352GEB/V Wolfson Microelectronics, WM8352GEB/V Datasheet - Page 292

• Manufacturer Part Number: WM8352GEB/V
• Description: Audio CODECs Audio CODEC plus pwr management
• Manufacturer: Wolfson Microelectronics

Specifications of WM8352GEB/V

• Number Of Adc Inputs: 2
• Number Of Dac Outputs: 2
• Conversion Rate: 48 KSPS
• Interface Type: Serial (2-Wire, 3-Wire, 4-Wire)
• Resolution: 12 bit
• Operating Supply Voltage: 3.7 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: BGA
• Minimum Operating Temperature: - 25 C
• Number Of Channels: 2 ADC/2 DAC
• Supply Current: 260 uA
• Thd Plus Noise: - 83 dB
• Audio Codec Type: Stereo
• No. Of Adcs: 2
• No. Of Dacs: 2
• No. Of Input Channels: 8
• No. Of Output Channels: 6
• Adc / Dac Resolution: 24bit
• Adcs / Dacs Signal To Noise Ratio: 95dB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

WM8352
Register B0h DCDC/LDO requested
w
REGISTER
REGISTER
ADDRESS
ADDRESS
R177 (B1h)
options
DCDC
Active
13:12
BIT
BIT
15
5
3
2
2
1
0
DCDC_DISCLKS
DC6_ACTIVE
DC4_ACTIVE
DC3_ACTIVE
DC3_ENA
DC2_ENA
DC1_ENA
LABEL
PUTO[1:0]
LABEL
DEFAULT
DEFAULT
0
0
0
00
0
1
1
1
Reset by state machine. Default held in metal mask.
DCDC3 converter enable
0 = disabled
1 = enabled
Note: internal conditions may prevent the converter
from actually switching on - see DCDC/LDO Status
register for actual converter status.
Reset by state machine. Default held in metal mask.
DCDC2 converter enable
0 = disabled
1 = enabled
Note: internal conditions may prevent the converter
from actually switching on - see DCDC/LDO Status
register for actual converter status.
Reset by state machine. Default held in metal mask.
DCDC1 converter enable
0 = disabled
1 = enabled
Note: internal conditions may prevent the converter
from actually switching on - see DCDC/LDO Status
register for actual converter status.
Reset by state machine. Default held in metal mask.
DCDC clock enable
0 = DCDC Clocks enabled
1 = DCDC1, 3, 4 and 6 clocks disabled.
Note: This feature is useful in reducing the current
consumption if all 4 DCDCs are in LDO mode. The
requirement is to put them in LDO mode and then at
least 100us is required before clocks are disabled.
Again while coming out of LDO mode first enable the
clocks and then at least 100us wait and then come
out of LDO mode. This can only be used if the
processor is alive to set and unset this bit.
Reset by state machine.
Power up time out value for all converters
00 = 0.5ms
01 = 2ms
10 = 32ms
11 = 256ms
Reset by state machine.
DC-DC 6 Active mode
0 = Select Standby mode
1 = Select Active mode
Reset by state machine.
DC-DC 4 Active mode
0 = Select Standby mode
1 = Select Active mode
Reset by state machine.
DC-DC 3 Active mode
0 = Select Standby mode
1 = Select Active mode
DESCRIPTION
DESCRIPTION
PD, March 2010, Rev 4.2
REFER TO
REFER TO
Production Data
292