WM8352GEB/V Wolfson Microelectronics, WM8352GEB/V Datasheet - Page 183

• Manufacturer Part Number: WM8352GEB/V
• Description: Audio CODECs Audio CODEC plus pwr management
• Manufacturer: Wolfson Microelectronics

Specifications of WM8352GEB/V

• Number Of Adc Inputs: 2
• Number Of Dac Outputs: 2
• Conversion Rate: 48 KSPS
• Interface Type: Serial (2-Wire, 3-Wire, 4-Wire)
• Resolution: 12 bit
• Operating Supply Voltage: 3.7 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: BGA
• Minimum Operating Temperature: - 25 C
• Number Of Channels: 2 ADC/2 DAC
• Supply Current: 260 uA
• Thd Plus Noise: - 83 dB
• Audio Codec Type: Stereo
• No. Of Adcs: 2
• No. Of Dacs: 2
• No. Of Input Channels: 8
• No. Of Output Channels: 6
• Adc / Dac Resolution: 24bit
• Adcs / Dacs Signal To Noise Ratio: 95dB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Production Data
w
/WAKEUP
32kHz
ADA
ADCLRCLK
ADCLRCLKB
ADCBCLK
/BATT_FAULT
CH_IND
CODEC_OPCLK
DO_CONF
FLASH_OUT
FLL_CLK
ISINKC
ISINKD
ISINKE
LINE_SW
LINE_GT_BATT
MICDET
MICSHT
FUNCTION NAME
ALTERNATE
Input
Input
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
OUTPUT
INPUT /
Logic input signal causes wakeup from OFF or
HIBERNATE states. Can be used for accessory detection.
See Section 14.
32kHz clock input to Real Time Clock. See Section 22.
Aux ADC external data available signal. See Section 19.
0 = AUXADC external data not available
1 = AUXADC external data available
Alternate Left/Right clock for CODEC ADC digital interface.
When this function is selected, the LRCLK pin supports the
DAC interface only, and GPIO5 provides the ADC digital
interface L/R clock. See Section 12.
Inverted Left/Right clock for CODEC ADC digital interface.
When this function is selected, the LRCLK pin supports the
DAC interface only, and GPIO6 provides the inverted ADC
digital interface L/R clock. See Section 12.
Alternate BCLK for CODEC ADC digital interface. When
this function is selected, the BCLK pin supports the DAC
interface only, and GPIO8 provides the ADC digital
interface BCLK signal. See Section 12.
Same as /UVLO signal – indicates no power present.
Should be output as soon as possible after /UVLO.
Battery Charge status indication. This output can drive an
LED, which indicates battery charging status through
different flash rates. See Section 17.
Output clock from CODEC. Frequency is determined by
OPCLK_DIV. See Section 12.
Output used for development mode programming. Signal
goes high to indicate that external programming can take
place (during the Pre-Active state). Same functionality as
PWR_ON (GPIO output) but with additional programmable
option to prevent reset in OFF mode. See Section 14.
Logic output asserted for the duration of a Flash. Triggered
by either SINKA or SINKB; Triggered by GPIO or
CSn_FLASH bit. See Section 16.
Output FLL clock. See Section 12.4.
Open-drain output which can be used to drive LEDs
connected to LINE via a series resistor. See Section 16.
Open-drain output which can be used to drive LEDs
connected to LINE via a series resistor. See Section 16.
Open-drain output which can be used to drive LEDs
connected to LINE via a series resistor. See Section 16.
Used to drive an external PFET between ‘Wall’ supply and
LINE input, in order to prevent reverse conduction when
the Wall Adapter is disconnected. See Section 17.1.
Output to enable external PFET to reduce IR loses when
LINE is greater than BATT
Logic output indicating microphone bias current detection.
0 = Mic Bias Current not detected
1 = Mic Bias Current detected
Note that an Interrupt is also generated by this event. See
Section 13.12.2.
Logic output indicating microphone bias short circuit
detection.
0 = Mic Bias Short Circuit not detected
1 = Mic Bias Short Circuit detected
Note that an Interrupt is also generated by this event. See
Section 13.12.2.
DESCRIPTION
PD, March 2010, Rev 4.2
WM8352
183