FIN210ACMLX Fairchild Semiconductor, FIN210ACMLX Datasheet - Page 8

• Manufacturer Part Number: FIN210ACMLX
• Description: IC SER/DES 10BIT 32-MLP
• Manufacturer: Fairchild Semiconductor

Specifications of FIN210ACMLX

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Application Diagrams
© 2009 Fairchild Semiconductor Corporation
FIN210AC • Rev. 1.0.3
MASTER CLK
Baseban d
Processor
Baseband
Processor
PIXEL CLK
YUV[7:0]
SYS CLK
Data[7:0]
HSYNC
VSYNC
/RES
/RES
/CS0
Figure 7. 8-Bit WRITE-Only Microcontroller Interface (Example Shows BGA 42-Pin Package)
Serializer Configuration:
18MHz to 48MHz Frequency Range (S1=0, S0=1)
Normal Mode (PLL1=0; PLL0=1)
Master clock bypass mode.
Serializer Configuration:
18MHz to 48MHz Frequency Range (S1=0, S0=1)
CKREF is twice as fast STROBE (PLL1=1; PLL0=0)
CKREF=26MHz & STROBE Frequency=10 MHz
/WE
A0
VDDP1
Figure 6. 8-Bit YUV 1.3MPixel CMOS Imager In Clock Pass-Through Mode
B3:E1
E2
F1
NC
B3:E1
A6
B5
C1
E2
F1
F6
G3
G4
A3
G5
G6
A4
A6
B5
C1
F6
G3
G4
A4
G5
G6
CKREF
STROBE
CKP
DP[8:1]
DP[9]
DP[10]
/ENZ
DIRI
PWS1
PWS0
XTRM
S1
S0
D3
VDDP1
CKREF
STROBE
CKP
DP[8:1]
DP[9]
DP[10]
DIRI
PLL1
PLL0
CTL_ADJ
S1
S0
VDDP
(Continued)
D3
VDDP1
Dese rializer
VDDP
FIN210AC
GND
FIN210AC
Serializer
GND
VDDS/A
E4
CKSO+
CKSO-
CKSI+
/DIRO
CKSI-
DSI+
DSI-
VDDS/A
E4
CKSO+
CKSO-
CKSI+
/DIRO
DSO+
F4
CKSI-
DSO-
C5
C6
D5
D6
E6
E5
B6
F4
NC
VDD
C5
C6
D6
D5
E6
E5
B6
NC
NC NC
NC
NC
E5
E6
D6
D5
VDD
C6
C5
B6
NC
NC
CKSI+
CKSI-
DSO+
DSO-
CKSO-
CKSO+
/DIRO
E5
E6
D5
D6
C6
C5
B6
E4
VDDS/A
8
FIN210AC
Serializer
CKSI+
CKSI-
DSI+
DSI-
CKSO-
CKSO+
/DIRO
Deserializer Configuration:
~2 – 3ns output edge rates (S1=0, S0=1)
~50% CKP PW,(PWS1=PWS0=0)
Deserializer Configuration:
~7 – 8ns output edge rates (S1=1, S0=0)
~50% CKP PW,(PWS1=PWS0=0)
GND
E4
F4
VDDS/A
Deserializer
FIN210AC
CTL_ADJ
STROBE
VDDP
CKREF
DP[8:1]
VDDP2
DP[10]
GND
DP[9]
F4
D3
PLL1
PLL0
CKP
DIRI
S1
S0
STROBE
VDDP
CKREF
DP[8:1]
VDDP2
DP[10]
F6
G3
G4
A4
G5
G6
XTRM
PWS1
PWS0
DP[9]
C1
A6
B5
D3
/ENZ
B3:E1
E2
F1
CKP
DIRI
S1
S0
VDDP2
A4
A3
F6
G3
G4
G5
G6
E2
F1
C1
A6
B5
B3:E1
MASTER CLK
PIXEL CLK
YUV[7:0]
HSYNC
VSYNC
/RES
MAIN LCD
/WE
DATA[7:0]
A0
/CS
/RES
Camera Module
www.fairchildsemi.com