FIN210ACMLX Fairchild Semiconductor, FIN210ACMLX Datasheet
FIN210ACMLX
Specifications of FIN210ACMLX
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FIN210ACMLX Summary of contents
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... Fairchild’s proprietary ultra-low power, low- <10µA EMI technology. 2.8 to 3.6V 1.65 to 3.6V 15kV Applications 32-Terminal MLP 42-Ball USS-BGA Slider, Folder, & Clamshell Mobile Handsets FIN210ACMLX Printers FIN210ACGFX Security Cameras Related Resources For samples and questions, please contact: Interface@fairchildsemi.com. Internal Termination FIN210AC ...
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... DP[10] GND N/C VDDA G GND N/C PLL1 PLL0 42-Ball BGA, 3.5 x 4.5mm, .5mm pitch (Top View) Figure 2. FIN210AC (Serializer DIRI=1) Pin Assignments (Top View) © 2009 Fairchild Semiconductor Corporation FIN210AC • Rev. 1.0.3 Description 5 6 N/C CKREF STROBE /DIRO DP[4] 1 DP[5] 2 ...
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... DP[10] N/C N/C VDDA G N/C N/C PWS1 PWS0 42-Ball BGA, 3.5 x 4.5mm, .5mm pitch (Top View) Figure 3. FIN210AC (Deserializer DIRI=0) Pin Assignments (Top View) © 2009 Fairchild Semiconductor Corporation FIN210AC • Rev. 1.0.3 Description 5 6 N/C CKREF STROBE /DIRO DP[4] 1 DP[5] 2 ...
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... Non-Inverted 138.9ns Non-Inverted 26ns Inverted 26ns Non-Inverted 52.1ns Non-Inverted 69.4ns Power-Down © 2009 Fairchild Semiconductor Corporation FIN210AC • Rev. 1.0.3 Function CKREF STROBE Slow Frequencies 5MHz to 15MHz ≤ CKREF (Up to 15MHz) 5MHz to 14.2MHz ≤ CKREF (Up to 14.2MHz) 5MHz to 15MHz ≤ CKREF / 2 (Up to 7.5MHz) 5MHz to 15MHz ≤ ...
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... Table 5 indicates the state of the input states and output buffers in Power-Down mode. Table 5. Power-Down Signal Pins DIRI=1 (Serializer) DP[1:10] Inputs Disabled CKP STROBE Input Disabled CKREF Input Disabled /DIRO © 2009 Fairchild Semiconductor Corporation FIN210AC • Rev. 1.0 8ns (C = 8pF 5ns (C = 8pF 3ns (C = 8pF) L PLL1 PWS0 ...
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... Connect master clock to STROBE (BGA pin B5) Serializer Configuration (DIRI=1) 1. CKSI passes master clock to CKP output (BGA pin C1) © 2009 Fairchild Semiconductor Corporation FIN210AC • Rev. 1.0.3 CKREF and STROBE Signals Please note that there is a setup and hold time between STROBE and data that must be met as seen on the electrical characteristics section ...
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... PWS0 A3 XTRM GND /RES Figure 5. 8-Bit YUV 1.3MPixel CMOS Imager (Example Shows BGA 42-Pin Package) Deserializer Configuration: ~2 – 3ns output edge rates (S1=0, S0=1) ~50% CKP PW,(PWS1=PWS0=0) © 2009 Fairchild Semiconductor Corporation FIN210AC • Rev. 1.0.3 FIN210AC Deserializer VDD VDDS/A VDDS CKSO+ ...
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... Figure 7. 8-Bit WRITE-Only Microcontroller Interface (Example Shows BGA 42-Pin Package) Serializer Configuration: 18MHz to 48MHz Frequency Range (S1=0, S0=1) CKREF is twice as fast STROBE (PLL1=1; PLL0=0) CKREF=26MHz & STROBE Frequency=10 MHz © 2009 Fairchild Semiconductor Corporation FIN210AC • Rev. 1.0.3 FIN210AC Serializer VDD ...
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... Do not place test points on differential serial wires. Use differential serial wires a minimum of 2cm away from the antenna. For additional applications notes or flex guidelines see your sales representative or contact Fairchild directly. For samples and questions, please contact: Interface@fairchildsemi.com. © 2009 Fairchild Semiconductor Corporation FIN210AC • Rev. 1.0.3 9 www.fairchildsemi.com ...
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... Absolute Maximum Ratings. Symbol Supply Voltage DDA DDS V Supply Voltage DDP T Operating Temperature A V Supply Noise Voltage DDA-PP © 2009 Fairchild Semiconductor Corporation FIN210AC • Rev. 1.0.3 Parameter Serial I/O Pins to GND All Pins Parameter 10 Min. Max. Unit -0.5V +4.6 -0.5 V +0.5 DD ...
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... Power Supply Currents Symbol Parameter I V Power-Down Supply Current DD_PD DD Dynamic Serializer Power Supply I DD_SER1 Current Dynamic Deserializer Power Supply I DD_DES1 Current © 2009 Fairchild Semiconductor Corporation FIN210AC • Rev. 1.0.3 Test Conditions I =-2.0mA, S1=0,S0 =-0.4mA, S1=1,S0 =-1.0mA, S1=1,S0 =2.0mA, S1=0,S0 ...
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... Output Delay Phase Lock Loop (PLL) AC Electrical Characteristics t Serializer PLL Stabilization Time TPLLS0 t PLL Disable Time Loss of Clock TPLLD0 t PLL Power-Down Time TPLLD1 © 2009 Fairchild Semiconductor Corporation FIN210AC • Rev. 1.0.3 Test Conditions DIRI=1, S1=0, S0=0, V =2.5V DD Test Conditions S1=0, S0 ...
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... PHZ Deserializer Disable Time LOW to DPTri-State; DIRI=0, t DISDES DISDES DP Note: If S0(2) is transitioning, S1(1) must =0 for test to be valid. t Serializer Disable Time LOW to CKP HIGH DISSER © 2009 Fairchild Semiconductor Corporation FIN210AC • Rev. 1.0.3 (Continued) Test Conditions PWS1 t PDV = STRB CKREF ...
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... A, B, and C). MLP Shipping Reel Dimensions 10° maximum component rotation Sketch A (Side or Front Sectional View) Component Rotation Dia A max Dia A Dim B Tape Width Max. Min. 8 330.0 1.5 12 330.0 1.5 16 330.0 1.5 © 2009 Fairchild Semiconductor Corporation FIN210AC • Rev. 1.0 Min. ±0.1 ± ...
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... Figure 9. 32-Lead, Molded Leadless Package (MLP) Operating Order Number Temperature Range FIN210ACMLX -30 to 70°C For Fairchild’s definition of Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html. Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’ ...
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... Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’ ...
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... Fairchild Semiconductor Corporation FIN210AC • Rev. 1.0.3 17 www.fairchildsemi.com ...