FIN210ACMLX Fairchild Semiconductor, FIN210ACMLX Datasheet - Page 7

• Manufacturer Part Number: FIN210ACMLX
• Description: IC SER/DES 10BIT 32-MLP
• Manufacturer: Fairchild Semiconductor

Specifications of FIN210ACMLX

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Application Diagrams
The following application diagrams illustrate the most typical applications for the FIN210 device. Specific configurations of the
control pins may vary based on the needs of a given system. The following recommendations are valid for all of the
applications shown.
© 2009 Fairchild Semiconductor Corporation
FIN210AC • Rev. 1.0.3
MASTER CLK
Baseban d
Processor
Baseband
Processor
PIXEL CLK
PIXEL CLK
YUV[7:0]
Data[7:0]
HSYNC
VSYNC
HSYNC
VSYNC
/RES
/RES
Serializer Configuration:
10MHz to 30MHz Frequency Range (S1=S0=1)
Normal Mode (PLL1=0; PLL0=1)
Deserializer Configuration:
~2 – 3ns output edge rates (S1=0, S0=1)
~50% CKP PW,(PWS1=PWS0=0)
Figure 5. 8-Bit YUV 1.3MPixel CMOS Imager (Example Shows BGA 42-Pin Package)
VDDP1
NC
B3:E1
E2
F1
B3:E1
E2
F1
A6
B5
C1
Figure 4. 8-Bit RGB Application (Example Shows BGA 42-Pin Package)
F6
G3
G4
A3
G5
G6
A4
A6
B5
C1
F6
G3
G4
A4
G5
G6
CKREF
STROBE
CKP
DP[8:1]
DP[9]
DP[10]
/ENZ
DIRI
PWS1
PWS0
XTRM
S1
S0
D3
VDDP1
CKREF
STROBE
CKP
DP[8:1]
DP[9]
DP[10]
DIRI
PLL1
PLL0
CTL_ADJ
S1
S0
D3
VDDP
VDDP1
VDDP
Dese rializer
FIN210AC
GND
FIN210AC
Serializer
GND
VDDS/A
E4
CKSO+
CKSO-
CKSI+
/DIRO
CKSI-
DSI+
E4
VDDS/A
DSI-
CKSO+
CKSO-
CKSI+
DSO+
/DIRO
CKSI-
DSO-
F4
F4
C5
C6
D5
D6
E6
E5
B6
NC
C5
C6
D6
D5
E6
E5
B6
VDD
NC
NC
NC NC
NC
E5
E6
D6
D5
VDD
C6
C5
B6
NC
NC
E5
E6
D5
D6
CKSI+
CKSI-
DSO+
DSO-
CKSO-
CKSO+
/DIRO
C6
C5
B6
E4
VDDS/A
7
FIN210AC
CKSI+
CKSI-
DSI+
DSI-
CKSO-
CKSO+
/DIRO
Serializer
Deserializer Configuration:
~4 – 5ns output edge rates (S1=S0=1)
~50% CKP PW,(PWS1=PWS0=0)
Serializer Configuration:
18MHz to 48MHz Frequency Range (S1=0, S0=1)
Normal Mode (PLL1=0, PLL0=1)
E4
VDDS/A
GND
F4
Deserializer
FIN210AC
CTL_ADJ
STROBE
VDDP
CKREF
DP[8:1]
GND
VDDP2
DP[10]
F4
DP[9]
D3
PLL1
PLL0
CKP
DIRI
S1
S0
STROBE
VDDP
CKREF
DP[8:1]
VDDP2
DP[10]
PWS1
PWS0
XTRM
F6
G3
G4
A4
G5
G6
DP[9]
D3
/ENZ
CKP
DIRI
C1
A6
B5
B3:E1
E2
F1
S1
S0
VDDP2
A4
A3
F6
G3
G4
G5
G6
C1
A6
B5
B3:E1
E2
F1
MASTER CLK
PIXEL CLK
YUV[7:0]
HSYNC
VSYNC
/RES
PIXEL CLK
Data[7:0]
HSYNC
VSYNC
/RES
LCD MODULE
Camera Module
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