SI4431-A0-FM Silicon Laboratories Inc, SI4431-A0-FM Datasheet - Page 92

• Manufacturer Part Number: SI4431-A0-FM
• Description: IC TXRX ISM 930MHZ 3.6V 20-QFN
• Manufacturer: Silicon Laboratories Inc

Specifications of SI4431-A0-FM

• Package / Case: 20-QFN
• Mfg Application Notes: Transitioning SI4430/31 to Rev B
• Frequency: 240MHz ~ 930MHz
• Data Rate - Maximum: 128kbps
• Modulation Or Protocol: FSK, GFSK, OOK
• Power - Output: 13dBm
• Sensitivity: -118dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 18.5mA
• Current - Transmitting: 28mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Number Of Receivers: 2
• Number Of Transmitters: 1
• Wireless Frequency: 240 MHz to 930 MHz
• Output Power: 13 dBm
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Maximum Supply Current: 28 mA
• Minimum Operating Temperature: - 40 C
• Modulation: FSK, GFSK, OOK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Applications: -
• Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 336-1633-5

Register 08h. Operating Mode and Function Control 2
Si4431
Reset value = 00000000
92
Name
Type
Bit
7:5
Bit
4
3
2
1
0
antdiv[2:0]
Name
rxmpk
autotx
enldm
D7
ffclrrx
ffclrtx
antdiv[2:0]
Enable Antenna Diversity.
The GPIO must be configured for Antenna Diversity for the algorithm to work properly.
000:
001:
010:
011:
100:
101:
110:
111:
RX Multi Packet.
When the chip is selected to use FIFO Mode (dtmod[1:0]) and RX Packet Handling
(enpacrx) then it will fill up the FIFO with multiple valid packets if this bit is set, otherwise
the transceiver will automatically leave the RX State after the first valid packet has been
received.
Automatic Transmission.
When autotx = 1 the transceiver will enter automatically TX State when the FIFO is
almost full. When the FIFO is empty it will automatically return to the Idle State.
Enable Low Duty Cycle Mode.
If this bit is set to 1 then the chip turns on the RX regularly. The frequency should be set
in the Wake-Up Timer Period register, while the minimum ON time should be set in the
Low-Duty Cycle Mode Duration register. The FIFO mode should be enabled also.
RX FIFO Reset/Clear.
This has to be a two writes operation: Setting ffclrrx =1 followed by ffclrrx = 0 will clear the
contents of the RX FIFO.
TX FIFO Reset/Clear.
This has to be a two writes operation: Setting ffclrtx =1 followed by ffclrtx = 0 will clear the
contents of the TX FIFO.
R/W
D6
RX/TX state
GPIO Ant1
0
1
0
1
antenna diversity algorithm
antenna diversity algorithm
ant. div. algorithm in beacon mode
ant. div. algorithm in beacon mode
D5
Preliminary Rev. 0.4
rxmpk
R/W
D4
Function
autotx
R/W
D3
non RX/TX state
GPIO Ant2
1
0
1
0
0
1
0
1
enldm
R/W
D2
GPIO Ant1 GPIO Ant2
0
0
1
1
0
1
0
1
ffclrrx
R/W
D1
0
0
1
1
ffclrtx
R/W
D0