SI4431-A0-FM Silicon Laboratories Inc, SI4431-A0-FM Datasheet - Page 142

• Manufacturer Part Number: SI4431-A0-FM
• Description: IC TXRX ISM 930MHZ 3.6V 20-QFN
• Manufacturer: Silicon Laboratories Inc

Specifications of SI4431-A0-FM

• Package / Case: 20-QFN
• Mfg Application Notes: Transitioning SI4430/31 to Rev B
• Frequency: 240MHz ~ 930MHz
• Data Rate - Maximum: 128kbps
• Modulation Or Protocol: FSK, GFSK, OOK
• Power - Output: 13dBm
• Sensitivity: -118dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 18.5mA
• Current - Transmitting: 28mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Number Of Receivers: 2
• Number Of Transmitters: 1
• Wireless Frequency: 240 MHz to 930 MHz
• Output Power: 13 dBm
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Maximum Supply Current: 28 mA
• Minimum Operating Temperature: - 40 C
• Modulation: FSK, GFSK, OOK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Applications: -
• Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 336-1633-5

Register 65h. LDO Control Override
Register 66h. LDO Level Settings
Si4431
Reset value = 10000001
Reset value = 00000011
142
Name
Name
Type
Type
Bit
Bit
2:0
Bit
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
endigpwdn
Reserved
enspor
envcoldo
endigldo
enovr
enpllldo
R/W
enspor
enrfldo
R/W
enrc32
enbias
enifldo
Name
Name
enxtal
D7
D7
enovr
diglvl
ents
Smart POR Enable.
Bias Enable.
VCO LDO Enable.
IF LDO Enable.
RF LDO Enable.
PLL LDO Enable.
Digital LDO Enable.
Digital Power Domain Powerdown Enable in Idle Mode.
Enable Overrides.
If high, ovr values are output to the blocks and can enable or disable them, if low, some
ovr value can only enable the blocks.
Xtal Override Enable Value.
Temperature Sensor Enable.
32K Oscillator Enable.
Reserved.
Digital LDO Level Setting.
enbias
enxtal
R/W
R/W
D6
D6
envcoldo
R/W
R/W
ents
D5
D5
Preliminary Rev. 0.4
enrc32
enifldo
R/W
R/W
D4
D4
Reserved
Function
Function
enrfldo
R/W
D3
D3
R
enpllldo
R/W
D2
D2
endigldo
diglvl
R/W
R/W
D1
D1
endigpwdn
R/W
D0
D0