SI4431-A0-FM Silicon Laboratories Inc, SI4431-A0-FM Datasheet - Page 20

• Manufacturer Part Number: SI4431-A0-FM
• Description: IC TXRX ISM 930MHZ 3.6V 20-QFN
• Manufacturer: Silicon Laboratories Inc

Specifications of SI4431-A0-FM

• Package / Case: 20-QFN
• Mfg Application Notes: Transitioning SI4430/31 to Rev B
• Frequency: 240MHz ~ 930MHz
• Data Rate - Maximum: 128kbps
• Modulation Or Protocol: FSK, GFSK, OOK
• Power - Output: 13dBm
• Sensitivity: -118dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 18.5mA
• Current - Transmitting: 28mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Number Of Receivers: 2
• Number Of Transmitters: 1
• Wireless Frequency: 240 MHz to 930 MHz
• Output Power: 13 dBm
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Maximum Supply Current: 28 mA
• Minimum Operating Temperature: - 40 C
• Modulation: FSK, GFSK, OOK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Applications: -
• Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 336-1633-5

Si4431
The SPI interface contains a burst read/write mode which will allows for reading/writing sequential registers without
having to re-send the SPI address. When the nSEL bit is held low while continuing to send SCLK pulses, the SPI
interface will automatically increment the ADDR and read from/write to the next address. An SPI burst write
transaction is demonstrated in Figure 4 and burst read in Figure 3. As long as nSEL is held low, input data will be
latched into the Si4431 every eight SCLK cycles. A burst read transaction is also demonstrated in Figure 5.
20
SDO
SCLK
nSEL
SCLK
nSEL
SDI
SDI
First Bit
First Bit
RW
RW
=1
=0
SDO
SCLK
nSEL
SDI
A6
A6
A5
A5
First Bit
A4
A4
RW
=0
A3
A3
A6
A2
A2
Figure 4. SPI Timing—Burst Write Mode
Figure 5. SPI Timing—Burst Read Mode
A5
Figure 3. SPI Timing—READ Mode
A1
A1
A4
First Bit
A0
A0
A3
D7
=X
D7
D7
=X
A2
Preliminary Rev. 0.4
D6 D5 D4 D3
D6
=X
D6
=X
A1
D5
=X
D5
=X
First Bit
A0
D4
=X
D4
=X
D7
D7
=X
D3
=X
D3
=X
D6 D5 D4 D3
D6
=X
D2
=X
D2
=X
D2 D1 D0
D5
=X
Last Bit
D1
=X
D1
=X
D4
=X
D0
=X
D0
=X
D3
=X
D7
=X
D7 D6 D5 D4 D3
D2
=X
D2 D1 D0
D6
=X
D1
=X
D5
=X
Last Bit
D0
=X
Last Bit
D4
=X
D3
=X
D2
=X
D2 D1 D0
D1
=X
Last Bit
D0
=X