SI4431-A0-FM Silicon Laboratories Inc, SI4431-A0-FM Datasheet - Page 39

• Manufacturer Part Number: SI4431-A0-FM
• Description: IC TXRX ISM 930MHZ 3.6V 20-QFN
• Manufacturer: Silicon Laboratories Inc

Specifications of SI4431-A0-FM

• Package / Case: 20-QFN
• Mfg Application Notes: Transitioning SI4430/31 to Rev B
• Frequency: 240MHz ~ 930MHz
• Data Rate - Maximum: 128kbps
• Modulation Or Protocol: FSK, GFSK, OOK
• Power - Output: 13dBm
• Sensitivity: -118dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 18.5mA
• Current - Transmitting: 28mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Number Of Receivers: 2
• Number Of Transmitters: 1
• Wireless Frequency: 240 MHz to 930 MHz
• Output Power: 13 dBm
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Maximum Supply Current: 28 mA
• Minimum Operating Temperature: - 40 C
• Modulation: FSK, GFSK, OOK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Applications: -
• Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 336-1633-5

Si4431
The Invalid Preamble Detector issues an interrupt when no valid preamble signal is found. After the receiver is
enabled, the Invalid Preamble Detector output is ignored for 16 Tb (Where Tb is the time of a bit duration) to allow
the receiver to settle. The Invalid Preamble Detect interrupt can be used to save power and speed-up search in
receive mode. It is advised to mask the invalid preamble interrupt when Antenna Diversity is enabled.
The Received Signal Strength Indicator (RSSI) provides a measure of the signal strength received on the tuned
channel. The resolution of the RSSI is 0.5 dB. This high resolution RSSI enables accurate channel power
measurements for clear channel assessment (CCA), carrier sense (CS), and listen before talk (LBT) functionality.
Frequency mistuning caused by crystal inaccuracies can be compensated by enabling the digital Automatic
Frequency Control (AFC) in receive mode.
TM
A comprehensive programmable Packet Handler including key features of Silicon Labs’ EZMac
is integrated to
create a variety of communication topologies ranging from peer-to-peer networks to mesh networks. The extensive
programmability of the packet header allows for advanced packet filtering which in turn enables a mix of broadcast,
group, and point-to-point communication.
A wireless communication channel can be corrupted by noise and interference, and it is therefore important to
know if the received data is free of errors. A cyclic redundancy check (CRC) is used to detect the presence of
erroneous bits in each packet. A CRC is computed and appended at the tail of each transmitted packet and verified
by the receiver to confirm that no errors have occurred. The Packet Handler and CRC are extremely valuable
features which can significantly reduce the load on the system microcontroller allowing for a simpler and cheaper
microcontroller.
The digital modem includes the TX Modulator which converts the TX Data bits into the corresponding stream of
digital modulation values to be summed with the fractional input to the sigma-delta modulator. This modulation
approach results in highly accurate resolution of the frequency deviation. A Gaussian filter is implemented to
support GFSK, considerably reducing the energy in the adjacent channels. The bandwidth-time product (BT) is 0.5
for all programmed data rates.
5.6. Synthesizer
An integrated Sigma Delta (ΣΔ) Fractional-N PLL synthesizer capable of operating from 240–930 MHz is provided
on-chip. Using a ΣΔ synthesizer has many advantages; it provides large amounts of flexibility in choosing data rate,
deviation, channel frequency, and channel spacing. The transmit modulation is applied directly to the loop in the
digital domain through the fractional divider which results in very precise accuracy and control over the transmit
deviation.
The PLL and - modulator scheme is designed to support any desired frequency and channel spacing in the
range from 240–930 MHz with a frequency resolution of 156.25 Hz (Low band) or 312.5 Hz (High band). The
transmit data rate can be programmed between 1–128 kbps, and the frequency deviation can be programmed
between ±1–160 kHz. These parameters may be adjusted via registers as shown in "3.6. Frequency Control" on
page 27.
TX
Selectable
Fref = 10 M
PFD
CP
LPF
RX
Divider
VCO
N
Delta-
TX
Modulation
Sigma
Figure 15. PLL Synthesizer Block Diagram
Preliminary Rev. 0.4
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