SI4431-A0-FM Silicon Laboratories Inc, SI4431-A0-FM Datasheet - Page 132

• Manufacturer Part Number: SI4431-A0-FM
• Description: IC TXRX ISM 930MHZ 3.6V 20-QFN
• Manufacturer: Silicon Laboratories Inc

Specifications of SI4431-A0-FM

• Package / Case: 20-QFN
• Mfg Application Notes: Transitioning SI4430/31 to Rev B
• Frequency: 240MHz ~ 930MHz
• Data Rate - Maximum: 128kbps
• Modulation Or Protocol: FSK, GFSK, OOK
• Power - Output: 13dBm
• Sensitivity: -118dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 18.5mA
• Current - Transmitting: 28mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Number Of Receivers: 2
• Number Of Transmitters: 1
• Wireless Frequency: 240 MHz to 930 MHz
• Output Power: 13 dBm
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Maximum Supply Current: 28 mA
• Minimum Operating Temperature: - 40 C
• Modulation: FSK, GFSK, OOK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Applications: -
• Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 336-1633-5

Register 53h. PLL Tune Time
Si4431
The total settling time (cold start) of the PLL after the calibration can be calculated as T
Reset value = 01010010
Reset value = 01010100
Invalid preamble will be evaluated during this period: (invalid_preamble_Threshold x 4) x Bit Rate period.
132
Register 54h. PA Boost
Name
Name
Type
Type
Bit
7:3
2:0
7:6
5:2
Bit
Bit
Bit
1
0
pa_vbias_boost PA VBIAS Boost.
inv_pre_th[5:2] Invalid Preamble Threshold.
Reserved[7:6]
ldo_pa_boost
pllts[4:0]
Name
D7
D7
pllt0
Name
Reserved[7:6]
R/W
PLL Soft Settling Time (T
This register will set the settling time for the PLL from a previous locked frequency in
Tune mode. The value is configurable between 0 µs and 310 µs, in 10 µs intervals. The
default plltime corresponds to 100 µs. See formula above.
PLL Settling Time (T
This register will set the time allowed for PLL settling after the calibrations are completed.
The value is configurable between 0 µs and 70 µs, in 10 µs steps. The default pllt0 corre-
sponds to 20 µs. See formula above.
D6
D6
Reserved.
LDO PA Boost.
pllts[4:0]
D5
R/W
D5
O
Preliminary Rev. 0.4
).
D4
S
).
D4
inv_pre_th
R/W
D3
Function
Function
D3
D2
D2
ldo_pa_boost pa_vbias_boost
CS
R/W
D1
= T
R/W
pllt0
D1
S
+ T
O
.
R/W
D0
D0