SI4431-A0-FM Silicon Laboratories Inc, SI4431-A0-FM Datasheet - Page 86

• Manufacturer Part Number: SI4431-A0-FM
• Description: IC TXRX ISM 930MHZ 3.6V 20-QFN
• Manufacturer: Silicon Laboratories Inc

Specifications of SI4431-A0-FM

• Package / Case: 20-QFN
• Mfg Application Notes: Transitioning SI4430/31 to Rev B
• Frequency: 240MHz ~ 930MHz
• Data Rate - Maximum: 128kbps
• Modulation Or Protocol: FSK, GFSK, OOK
• Power - Output: 13dBm
• Sensitivity: -118dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 18.5mA
• Current - Transmitting: 28mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Number Of Receivers: 2
• Number Of Transmitters: 1
• Wireless Frequency: 240 MHz to 930 MHz
• Output Power: 13 dBm
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Maximum Supply Current: 28 mA
• Minimum Operating Temperature: - 40 C
• Modulation: FSK, GFSK, OOK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Applications: -
• Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 336-1633-5

Si4431
86
Bit
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Table 30. When are Individual Status Bits Set/Cleared if not Enabled as Interrupts?
icrcerror
itxffaem
itxffafull
irxffafull
ipkvalid
ipksent
Status
Name
icrcerror
itxffaem
itxffafull
irxffafull
ipkvalid
ifferr
ipksent
Status
iext
Name
ifferr
iext
Set if there is a FIFO overflow or underflow. Cleared by applying FIFO reset.
Automatically cleared at the start of transmission when the number of bytes in the FIFO is
less than or equal to the threshold.
threshold. Automatically cleared when the number of data bytes in the TX FIFO is above the
Almost Empty threshold.
Set when the number of bytes in the RX FIFO is greater than the Almost Full threshold.
Cleared when the number of bytes in the RX FIFO is below the Almost Full threshold.
External interrupt source.
Set once a packet is successfully sent (no TX abort). Cleared upon leaving FIFO mode or at
the start of a new transmission.
Set up the successful reception of a packet (no RX abort). Cleared upon receiving and
acknowledging the Sync Word for the next packet.
Set if the CRC computed from the RX packet differs from the CRC in the TX packet. Cleared
at the start of reception for the next packet.
Set when the number of bytes written to TX FIFO is greater than the Almost Full threshold.
Set when the number of bytes in the TX FIFO is less than or equal to the Almost Empty
Set if there is a FIFO Overflow or Underflow. It is cleared only by applying FIFO reset to
the specific FIFO that caused the condition.
Will be set when the number of bytes written to TX FIFO is greater than the Almost Full
threshold set by SPI. It is automatically cleared when we start transmitting and the FIFO
data is read out and the number of bytes left in the FIFO is smaller or equal to the thresh-
old).
Will be set when the number of bytes (not yet transmitted) in TX FIFO is smaller or equal
than the Almost Empty threshold set by SPI. It is automatically cleared when we write
enough data to TX FIFO so that the number of data bytes not yet transmitted is above the
Almost Empty threshold.
Will be set when the number of bytes received (and not yet read-out) in RX FIFO is greater
than the Almost Full threshold set by SPI. It is automatically cleared when we read enough
data from RX FIFO so that the number of data bytes not yet read is below the Almost Full
threshold.
External interrupt source
Will go high once a packet is sent all the way through (no TX abort). This status will be
cleaned if 1) We leave FIFO mode or 2) In FIFO mode we start a new transmission.
Goes high once a packet is fully received (no RX abort). It is automatically cleaned once
we receive and acknowledge the Sync Word for the next packet.
Goes High once the CRC computed during RX differs from the CRC sent in the packet by
the TX. It is cleaned once we start receiving new data in the next packet.
Table 29. Interrupt or Status 1 Bit Set/Clear Description
Preliminary Rev. 0.4
Set/Clear Conditions
Set/Clear Conditions