SI4431-A0-FM Silicon Laboratories Inc, SI4431-A0-FM Datasheet - Page 53

• Manufacturer Part Number: SI4431-A0-FM
• Description: IC TXRX ISM 930MHZ 3.6V 20-QFN
• Manufacturer: Silicon Laboratories Inc

Specifications of SI4431-A0-FM

• Package / Case: 20-QFN
• Mfg Application Notes: Transitioning SI4430/31 to Rev B
• Frequency: 240MHz ~ 930MHz
• Data Rate - Maximum: 128kbps
• Modulation Or Protocol: FSK, GFSK, OOK
• Power - Output: 13dBm
• Sensitivity: -118dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 18.5mA
• Current - Transmitting: 28mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Number Of Receivers: 2
• Number Of Transmitters: 1
• Wireless Frequency: 240 MHz to 930 MHz
• Output Power: 13 dBm
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Maximum Supply Current: 28 mA
• Minimum Operating Temperature: - 40 C
• Modulation: FSK, GFSK, OOK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Applications: -
• Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 336-1633-5

The clock recovery oversampling rate is set via rxosr[10:0] in "Register 20h. Clock Recovery Oversampling Rate"
and "Register 21h. Clock Recovery Offset 2".
ndec_exp and dwn3_bypass together with the receive data rate (Rb) are used to calculate rxosr:
Where: Rb is in kbps and enmanch is the Manchester Coding parameter. The resulting rxdr[10:0] value should be
rounded to an integer hexadecimal number.
The clock recovery offset ncoff[19:0] in "Register 21h. Clock Recovery Offset 2", "Register 22h. Clock Recovery
Offset 1", and "Register 23h. Clock Recovery Offset 0" is calculated as follows:
Where: Rb is in kbps.
The clock recovery gain crgain[10:0] in "Register 24h. Clock Recovery Timing Loop Gain 1" and "Register 25h.
Clock Recovery Timing Loop Gain 0" is calculated as follows:
ncoff
rxosr
Rb(1+ enmanch) [kbps]
Min
40
0
1
2
3
8
Table 19. ndec[2:0] Settings


Rb
2
500
500
ndec
crgain
Preliminary Rev. 0.4

1 (
_


exp


1

1

enmanch

3



2
2
2 
Max
Rb

40
65

1
2
3
8
dwn
dwn

rxosr
2
1 (
)
16
3

3

_
_
2
enmanch
bypass
20
bypass

ndec[2:0]
ndec
_
exp
5
4
3
2
1
0


)
Si4431
53