MRF24J40-I/ML Microchip Technology, MRF24J40-I/ML Datasheet - Page 37

• Manufacturer Part Number: MRF24J40-I/ML
• Description: IC TXRX IEEE/ZIGBEE 2.4GHZ 40QFN
• Manufacturer: Microchip Technology

Specifications of MRF24J40-I/ML

• Package / Case: 40-QFN
• Frequency: 2.4GHz
• Data Rate - Maximum: 250kbps
• Modulation Or Protocol: 802.15.4
• Applications: ISM, ZigBee™
• Power - Output: 0dBm
• Sensitivity: -95dBm
• Voltage - Supply: 2.4 V ~ 3.6 V
• Current - Receiving: 18mA
• Current - Transmitting: 18mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Number Of Receivers: 1
• Number Of Transmitters: 1
• Wireless Frequency: 2.4 GHz
• Interface Type: 4 Wire SPI
• Noise Figure: 8 dB
• Output Power: + 0 dBm
• Operating Supply Voltage: 2.5 V, 3.3 V
• Maximum Operating Temperature: 85 C
• Mounting Style: SMD/SMT
• Maximum Supply Current: 22 mA
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

REGISTER 2-25:
© 2010 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
R/W-0
r
2:
3:
4:
Refer to IEEE 802.15.4™-2003 Standard, Section 7.2.1.1.3 “Frame Pending Subfield”.
Refer to IEEE 802.15.4-2003 Standard, Section 7.2.1.1.4 “Acknowledgement Request Subfield”.
Refer to IEEE 802.15.4-2003 Standard, Section 7.2.1.1.2 “Security Enabled Subfield”.
Bit is cleared at the next triggering of TXN FIFO.
Reserved: Maintain as ‘0’
FPSTAT: Frame Pending Status bit
Status of the frame pending bit in the received Acknowledgement frame.
1 = Sets frame pending bit
0 = Clears frame pending bit
INDIRECT: Activate Indirect Transmission bit (coordinator only)
1 = Indirect transmission enabled
0 = Indirect transmission disabled (default)
TXNACKREQ: TX Normal FIFO Acknowledgement Request bit
Transmit a frame with Acknowledgement frame expected. If Acknowledgement is not received,
retransmit.
1 = Acknowledgement requested
0 = No Acknowledgement requested (default)
TXNSECEN: TX Normal FIFO Security Enabled bit
1 = Security enabled
0 = Security disabled (default)
TXNTRIG: Transmit Frame in TX Normal FIFO bit
1 = Transmit the frame in the TX Normal FIFO; bit is automatically cleared by hardware
R/W-0
r
TXNCON: TRANSMIT NORMAL FIFO CONTROL REGISTER (ADDRESS: 0x1B)
r = reserved
W = Writable bit
‘1’ = Bit is set
R/W-0
r
FPSTAT
R-0
(1)
Preliminary
(1)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
INDIRECT
R/W-0
(4)
(3,4)
TXNACKREQ
R/W-0
(4)
(2,4)
(2,4)
x = Bit is unknown
TXNSECEN
MRF24J40
R/W-0
DS39776C-page 37
(3,4)
TXNTRIG
W-0
bit 0