MRF24J40-I/ML Microchip Technology, MRF24J40-I/ML Datasheet - Page 107

• Manufacturer Part Number: MRF24J40-I/ML
• Description: IC TXRX IEEE/ZIGBEE 2.4GHZ 40QFN
• Manufacturer: Microchip Technology

Specifications of MRF24J40-I/ML

• Package / Case: 40-QFN
• Frequency: 2.4GHz
• Data Rate - Maximum: 250kbps
• Modulation Or Protocol: 802.15.4
• Applications: ISM, ZigBee™
• Power - Output: 0dBm
• Sensitivity: -95dBm
• Voltage - Supply: 2.4 V ~ 3.6 V
• Current - Receiving: 18mA
• Current - Transmitting: 18mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Number Of Receivers: 1
• Number Of Transmitters: 1
• Wireless Frequency: 2.4 GHz
• Interface Type: 4 Wire SPI
• Noise Figure: 8 dB
• Output Power: + 0 dBm
• Operating Supply Voltage: 2.5 V, 3.3 V
• Maximum Operating Temperature: 85 C
• Mounting Style: SMD/SMT
• Maximum Supply Current: 22 mA
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

3.11
An IEEE 802.15.4 compliant packet is prefixed with a
Synchronization
preamble sequence and Start-of-Frame Delimiter
(SFD) fields. The preamble sequence enables the
receiver to achieve symbol synchronization.
The MRF24J40 monitors incoming signals and looks
for the preamble of IEEE 802.15.4 packets. When a
valid synchronization is obtained, the entire packet is
FIGURE 3-9:
© 2010 Microchip Technology Inc.
RXFIFO
From
Air
To
Reception
Packet to RXMAC
RXFIFO Address:
Packet Structure
RXFIFO
Packet
On Air
PHY
Header
PACKET RECEPTION
Preamble
(m+n+2)
Length
0x300
Frame
4
1
SHR
(SHR)
SFD
1
0x301 to (0x301 + m – 1)
Length
Frame
PHR
Header (MHR)
1
containing
m
Preliminary
the
PPDU
(0x301 + m) to (0x301 + m + n – 1)
PHY Payload
Data Payload (MSDU)
demodulated and the CRC is calculated and checked.
The packet is accepted or rejected depending on the
reception mode and frame filter, and placed in the
RXFIFO buffer. When the packet is placed in the
RXFIFO, a Receive Interrupt (RXIF 0x31<3>) is issued.
The RXFIFO address mapping is shown in Figure 3-9.
The following sections detail the reception operation of
the MRF24J40.
5 - 127
PSDU
n
FCS
Fields appended
by RXMAC
Fields removed
by RXMAC
2
(0x301 + m + n) to (0x301 + m + n + 1)
MRF24J40
RSSI
LQI
1
1
(0x301 + m + n + 2)
RSSI
RSSI
DS39776C-page 107
1
1
(0x301 + m + n + 3)
octets
octets