MRF24J40-I/ML Microchip Technology, MRF24J40-I/ML Datasheet - Page 29

• Manufacturer Part Number: MRF24J40-I/ML
• Description: IC TXRX IEEE/ZIGBEE 2.4GHZ 40QFN
• Manufacturer: Microchip Technology

Specifications of MRF24J40-I/ML

• Package / Case: 40-QFN
• Frequency: 2.4GHz
• Data Rate - Maximum: 250kbps
• Modulation Or Protocol: 802.15.4
• Applications: ISM, ZigBee™
• Power - Output: 0dBm
• Sensitivity: -95dBm
• Voltage - Supply: 2.4 V ~ 3.6 V
• Current - Receiving: 18mA
• Current - Transmitting: 18mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Number Of Receivers: 1
• Number Of Transmitters: 1
• Wireless Frequency: 2.4 GHz
• Interface Type: 4 Wire SPI
• Noise Figure: 8 dB
• Output Power: + 0 dBm
• Operating Supply Voltage: 2.5 V, 3.3 V
• Maximum Operating Temperature: 85 C
• Mounting Style: SMD/SMT
• Maximum Supply Current: 22 mA
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

REGISTER 2-15:
© 2010 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-4
bit 3-0
Note 1:
BO3
R/W-1
2:
(1)
Refer to IEEE 802.15.4™-2003 Standard, Section 7.5.1.1 “Superframe Structure”.
PANs that wish to use the superframe structure shall set macBeaconOrder to a value between 0 and 14
and macSuperframeOrder to a value between 0 and the value of macBeaconOrder
(i.e., 0 ≤ SO ≤ BO ≤ 14).
BO<3:0>: Beacon Order bits (macBeaconOrder)
Specifies how often the coordinator will transmit a beacon.
1111 = The coordinator will not transmit a beacon and the Superframe Order (SO) parameter value is
1110 = 14
•
•
•
0000 = 0
SO<3:0>: Superframe Order bits (macSuperframeOrder)
Specifies the length of the active portion of the superframe, including the beacon frame.
1111 = The superframe will not be active following the beacon (i.e., no active portion in the superframe
1110 = 14
•
•
•
0000 = 0
BO2
R/W-1
ORDER: BEACON AND SUPERFRAME ORDER REGISTER (ADDRESS: 0x10)
(1)
ignored (default)
(default))
W = Writable bit
‘1’ = Bit is set
BO1
R/W-1
(1)
BO0
R/W-1
Preliminary
(1)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
SO3
R/W-1
(1)
(1)
(2)
(1)
SO2
R/W-1
(1)
x = Bit is unknown
MRF24J40
SO1
R/W-1
(1)
DS39776C-page 29
(2)
SO0
R/W-1
(1)
bit 0