MRF24J40-I/ML Microchip Technology, MRF24J40-I/ML Datasheet - Page 112

• Manufacturer Part Number: MRF24J40-I/ML
• Description: IC TXRX IEEE/ZIGBEE 2.4GHZ 40QFN
• Manufacturer: Microchip Technology

Specifications of MRF24J40-I/ML

• Package / Case: 40-QFN
• Frequency: 2.4GHz
• Data Rate - Maximum: 250kbps
• Modulation Or Protocol: 802.15.4
• Applications: ISM, ZigBee™
• Power - Output: 0dBm
• Sensitivity: -95dBm
• Voltage - Supply: 2.4 V ~ 3.6 V
• Current - Receiving: 18mA
• Current - Transmitting: 18mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Number Of Receivers: 1
• Number Of Transmitters: 1
• Wireless Frequency: 2.4 GHz
• Interface Type: 4 Wire SPI
• Noise Figure: 8 dB
• Output Power: + 0 dBm
• Operating Supply Voltage: 2.5 V, 3.3 V
• Maximum Operating Temperature: 85 C
• Mounting Style: SMD/SMT
• Maximum Supply Current: 22 mA
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

3.12.1
The TX FIFOs are divided into four fields:
Header length – Used primarily in Security mode and
contains the length, in octets (bytes), of the MAC
Header (MHR). In Unsecure mode, this field is ignored.
Frame length – Contains the length, in octets (bytes),
of the MAC Header (MHR) and data payload.
Header – Contains the MAC Header (MHR).
Payload – Contains the data payload.
When the individual TX FIFO is triggered, the
MRF24J40 will handle transmitting the packet using the
CSMA-CA algorithm, Acknowledgment of the packet
(optional), retransmit if Acknowledgment not received
within required time period and interframe spacing. The
MRF24J40 will add the Synchronization Header
(SHR), PHY Header (PHR) and Frame Check
Sequence (FCS) automatically. If a packet is to be
FIGURE 3-12:
2.
3.
DS39776C-page 112
MRF24J40
Note:
Memory Address
Packet Structure
TX Normal FIFO
If the packet requires an Acknowledgment, the
Acknowledgment request bit in the frame control
field should be set to ‘1’ in the MAC Header
(MHR) when the host microcontroller loads the TX
Normal FIFO, and set the TXNACKREQ
(TXNCON
Section 3.13 “Acknowledgement” for more
information about Acknowledgment configuration.
If the frame is to be encrypted, the security
enabled bit in the frame control field should be
set to ‘1’ in the MAC Header (MHR) when the
host microcontroller loads the TX Normal FIFO,
and set the TXNSECEN (TXNCON 0x1B<1>)
bit = 1. Refer to Section 3.17 “Security” for
more information about Security modes.
TX FIFOs FRAME STRUCTURE
The header length field as implemented in
the MRF24J40 is 5-bits long. Therefore,
the header length maximum value is
31 octets (bytes).
octets
0x1B<2>)
Header
Length
TX NORMAL FIFO FORMAT
0x000
(m)
1
bit
(m + n)
Length
Frame
0x001
1
=
1.
0x002 – (0x002 + m – 1)
Refer
Header
m
to
Preliminary
transmitted using in-line security, the Message Integrity
Code (MIC) will be appended in the data payload by the
MRF24J40. Refer to Section 3.17 “Security” for more
information about transmitting and receiving data in
Security mode.
MRF24J40 will handle superframe timing, transmission
of the beacon and data packets during CAP and CFP.
3.12.2
In Beacon-Enabled mode, the TX Normal FIFO is used
for the transmission of data and MAC command frames
during the Contention Access Phase (CAP) of the
superframe.
In Nonbeacon-Enabled mode, the TX Normal FIFO is
used for all transmissions.
To transmit a packet in the TX Normal FIFO, perform
the following steps:
1.
4.
5.
The host processor loads the TX Normal FIFO
with IEEE 802.15.4 compliant data or MAC
command frame using the format shown in
Figure 3-12.
Transmit the packet by setting the TXNTRIG
(TXNCON 0x1B<0>) bit = 1. The bit will be
automatically cleared by hardware.
A TXNIF (INTSTAT 0x31<0>) interrupt will be
issued. The TXNSTAT (TXSTAT 0x24<0>) bit
indicates the status of the transmission:
TXNSTAT = 0: Transmission was successful
TXNSTAT = 1: Transmission failed, retry count
The number of retries of the most recent
transmission is contained in the TXNRETRY
(TXSTAT
(TXSTAT 0x24<5>) bit = 1 indicates if the failed
transmission was due to the channel busy
(CSMA-CA timed out).
(0x002 + m) – (0x002 + m + n – 1)
TX NORMAL FIFO
0x24<7:6>)
In Beacon-Enabled mode, the
exceeded
Payload
© 2010 Microchip Technology Inc.
n
bits.
The
CCAFAIL